Latch-up performance in cmos logic

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amin_8460

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hi there

What does it mean when the datasheet says:
"Latch-up performance exceeds 100 mA"
100 mA in where? IO or VCC? I already read the JEDEC standard but I could not clarify it for myself.
 

AFAIK this means: no latch-up for output currents up to 100mA .
 

Current into / out of any input pin and any standard logic
output pin, such that an isolation junction would become
forward biased (injecting substrate current). For example,
an input pin taken below ground will inject substrate current
through the ESD clamp network.
 

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