sgq03507
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Hi,
Latch up mechanism in CMOS inverter and CMOS amplifier is easy to understand.
It has been said that CMOS switch is much vulnerable and tend to go into SCR turn-on condition.
But for myself, latch up current flow in CMOS switch configuration is difficult to understand/find.
Could anyone please answer my question?
1) CMOS inverter case
This is easy to understand/perceive. In the Fig. 1 below, if drain potential of PMOS (OUT terminal) is higher than VDD + Vdiode as a red highlighted route, stray Q1 will trigger and current flows into stray Q2's base. Then SCR turn-on condition starts in red highlighted route (very low impedance) as in Fig. 2.
Figure 1
Figure 2
2) CMOS switch case
As a one example, let's consider a case that PMOS drain potential goes up (high voltage is applied) higher than VDD + Vdiode as in Fig 3. Regularly, in CMOS switch application, other end of the switch (in this case, source of N and P MOS) should be connected with high impedance load like next stage OP amp, high resistor or ADC.
Figure 3.
Q1 will turn on and large current flows through red highlighted route through Rsub but current to Q2 base is not large enough because its emitter (i.e. NMOS source terminal) load is Hi Z (bold/highlighted in blue) as in Fig 4.
As in Figure 5. after high voltage removed and returned to normal voltage condition, since Q2 collector load impedance is high, SCR turn-on condition should be soft. Further, Q1 base (= Vdd) will exceed Q1 emitter (= PMOS drain) voltage so Q1 will turn of after voltage returned to normal condition so SCR turn-on will not be generated.
Even Q2 collector current is high enough to turn well on Q1 making a SCR turn-on condition, since load impedance is high, large current inside the semiconductor would not flow I think.
Figure 4
Figure 5
So it is difficult to find the route of large current flow with SCR turn-on in CMOS switch fault condition.
Again, my question is, which route is it of high current flow when CMOS switch goes into SCR turn-on (CMOS switch fault) condition?
Of course, the other high current flow is expected when high voltage is applied but my question is SCR turn-on and continuous condition/behavior in CMOS switch configuration.
Please advise!
Latch up mechanism in CMOS inverter and CMOS amplifier is easy to understand.
It has been said that CMOS switch is much vulnerable and tend to go into SCR turn-on condition.
But for myself, latch up current flow in CMOS switch configuration is difficult to understand/find.
Could anyone please answer my question?
1) CMOS inverter case
This is easy to understand/perceive. In the Fig. 1 below, if drain potential of PMOS (OUT terminal) is higher than VDD + Vdiode as a red highlighted route, stray Q1 will trigger and current flows into stray Q2's base. Then SCR turn-on condition starts in red highlighted route (very low impedance) as in Fig. 2.
Figure 1
Figure 2
2) CMOS switch case
As a one example, let's consider a case that PMOS drain potential goes up (high voltage is applied) higher than VDD + Vdiode as in Fig 3. Regularly, in CMOS switch application, other end of the switch (in this case, source of N and P MOS) should be connected with high impedance load like next stage OP amp, high resistor or ADC.
Figure 3.
Q1 will turn on and large current flows through red highlighted route through Rsub but current to Q2 base is not large enough because its emitter (i.e. NMOS source terminal) load is Hi Z (bold/highlighted in blue) as in Fig 4.
As in Figure 5. after high voltage removed and returned to normal voltage condition, since Q2 collector load impedance is high, SCR turn-on condition should be soft. Further, Q1 base (= Vdd) will exceed Q1 emitter (= PMOS drain) voltage so Q1 will turn of after voltage returned to normal condition so SCR turn-on will not be generated.
Even Q2 collector current is high enough to turn well on Q1 making a SCR turn-on condition, since load impedance is high, large current inside the semiconductor would not flow I think.
Figure 4
Figure 5
So it is difficult to find the route of large current flow with SCR turn-on in CMOS switch fault condition.
Again, my question is, which route is it of high current flow when CMOS switch goes into SCR turn-on (CMOS switch fault) condition?
Of course, the other high current flow is expected when high voltage is applied but my question is SCR turn-on and continuous condition/behavior in CMOS switch configuration.
Please advise!
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