thenonbornking
Newbie level 4
Hi all, I am trying to generate the .lib file (timing and power characterization) for a large full-custom macro cell. I plan to use the macro in Cadence Encounter.
Is there a tool for automatically generating the .lib file from an extracted spice netlist?
The spice netlist for the full module is very large. In fact, spice cannot simulate the entire thing. We have had to simulate small parts of the circuit individually and then combine the information together to get first-order timing estimations.
I have looked into SignalStorm Library Characterizer but it seems to be focused on standard cells, which are much smaller than the large module I am working with.
FYI, the module is a 4-ported register file. We don't have a memory-compiler capable of generating 4-ported memories, so we have done a custom layout.
Any suggestions would be appreciated.
Thanks!
Is there a tool for automatically generating the .lib file from an extracted spice netlist?
The spice netlist for the full module is very large. In fact, spice cannot simulate the entire thing. We have had to simulate small parts of the circuit individually and then combine the information together to get first-order timing estimations.
I have looked into SignalStorm Library Characterizer but it seems to be focused on standard cells, which are much smaller than the large module I am working with.
FYI, the module is a 4-ported register file. We don't have a memory-compiler capable of generating 4-ported memories, so we have done a custom layout.
Any suggestions would be appreciated.
Thanks!