Large i/p Bandwidth Sigma-Delta ADC

[chanchg]

Hello Everyone,

Is is possible to design a Sig-Del ADC(probably switch-cap based) with following specs?

1. I/P Signal Bandwidth = 2.2Mhz
2. Conversion Rate = 8Mhz
3. Linearity = 16 bit

Process 0.13u TSMC or 0.18u TSMC.

Regards,
Chanchal

 

[Btrend]

Hello Everyone,

Is is possible to design a Sig-Del ADC(probably switch-cap based) with following specs?

1. I/P Signal Bandwidth = 2.2Mhz
2. Conversion Rate = 8Mhz
3. Linearity = 16 bit

Process 0.13u TSMC or 0.18u TSMC.

Regards,
Chanchal

according to ur spec.
f0=2.2M, fnyquist=4.4M, fc=8M
I try to deduce the require equation:
there is a ideal equation about SNR , OSR and order (N) of SDM.
the increasing bit of a N order SDM with every double of OSR is (N+0.5) bit.
so 16 =< 1+K(N+0.5)
1. if N=3 ===> K>=5 ===> choose K=5 the OSR should at lease 2^5=32
so u will need over sampling clock rate as fs=32*fnyquist= 140.8MHz ,
this spec. will be reflected to ur OP design of the modulator.
the minimal UGB of ur op will be 3*2fs= 844.8MHz.*
it is possible in .18u process. but more good in .13u process
2. if N=4 ===> K=4, OSR=2^4=16,
so u will need over sampling clock rate as fs=16*fnyquist= 70.4MHz
the minimal UGB of ur op will be 3*2fs= 422.4MHz.*
it is possible in .18u process.

there is a assumption above with *, that is the setting behavior of OP in S/H, cause there should exist gain error .

hopes this help u

 

[chanchg]

Thanks Btrend. I appreciate for your interest.
I forgot to mention that both the TSMC process I mentioned are digital 0.13/0.18 process. Is the data you mentioned is feasible for Switch-Cap? With 16 bit linearity+High Bandwidth, what topology of OTA you will suggest?


Regards,
Chanchg

 

[Btrend]

1. digital process is o.k. , but u need take more care about the parasitic cap.
2. sure, I was based on the assumption of SC circuit to derive those equations
3. I suggest u to find some document & paper on the IEEE paper , books of EDAboard . there exist many useful reference. before the choice of OTA topology , I think u should first define ur DC gain, current consumption, input common mode range, signal swing ..., these constrains will limit ur choice of topology.

Added after 34 seconds:

btw, what's the application of ur design?

 

[mr_chip]

Just a few more words added to Btrend's post:

if you choose N=4, OSR=16 & K=4, ideal equation will give you SNR of 103.4 dB while your requirement is 6.02*16+1.78=98.1 dB. Depending on the architecture you choose, you might get pretty close to theoretical 103.4 dB, but still you'll loose some SNR performance because of stability issues. Even more you'll loose because of fixed OTA gain & bandwidth, sampling clock jitter, noise in switches & OTA, switches non-linearity and other analog imperfections. So in my opinion you'll not get 16 bits from N=4, OSR=16 & K=4, 5 dB SNR margin is too small.

However I believe it should be possible to make a design in 0.18 CMOS fitting your spec, but you must first carefully consider analog imperfections & choose a proper architecture and make analog blocks' spec.

Hopefully power consumption is not a major concern in your design cause it'll be difficult to make a very low-power design for you spec.

 

[xwcwc1234]

What is the difference between converion rate fc and sampling clock arte fs?
By the way , what percentage of the settling time of this opmap should be choose , 0.01% or 0.1% or others ?

 

[avinash]

Hello Everyone,

Is is possible to design a Sig-Del ADC(probably switch-cap based) with following specs?

1. I/P Signal Bandwidth = 2.2Mhz
2. Conversion Rate = 8Mhz
3. Linearity = 16 bit

Process 0.13u TSMC or 0.18u TSMC.

Regards,
Chanchal

according to ur spec.
f0=2.2M, fnyquist=4.4M, fc=8M
I try to deduce the require equation:
there is a ideal equation about SNR , OSR and order (N) of SDM.
the increasing bit of a N order SDM with every double of OSR is (N+0.5) bit.
so 16 =< 1+K(N+0.5)
1. if N=3 ===> K>=5 ===> choose K=5 the OSR should at lease 2^5=32
so u will need over sampling clock rate as fs=32*fnyquist= 140.8MHz ,
this spec. will be reflected to ur OP design of the modulator.
the minimal UGB of ur op will be 3*2fs= 844.8MHz.*
it is possible in .18u process. but more good in .13u process
2. if N=4 ===> K=4, OSR=2^4=16,
so u will need over sampling clock rate as fs=16*fnyquist= 70.4MHz
the minimal UGB of ur op will be 3*2fs= 422.4MHz.*
it is possible in .18u process.

there is a assumption above with *, that is the setting behavior of OP in S/H, cause there should exist gain error .

hopes this help u

dear Btrend,
if sampling frequency is fs,why and how you have chosen opamp ugb=3*2fs
please explain.moreover what should be the gain of the opamp.In some literature i found that gain ≥ OSR .can you explain it.thanks in advance.

 

[neter]

Hi Btrend,

To be aimed at following Sigma-Delta ADC spec.How to do choice Single-Loop or Cascade Sigma-Delta structure ?

Thank you very much.

 

[schwang1970]

It is not easy to do it by SDM. OSR too small and signal bandwidth a littel large .
Had better by nyquist converter.