I'd start with simple time averaged current (@ max rated
freq) and see whether there is any interconnect overstress
that can be calculated. FETs tend to share pretty well. If
I had a per-finger current over about half reliability rating
I'd consider per-finger or maybe per-inverter ballasting.
Try fast corner, max temp for the current and min linewidth
electromigration calculations. As channels get shorter and
lower levels interconnect gets skinnier, it's more possible
to have devices that can't support their own weight, as it
were.
Sometimes (especially on old-school few-levels interconnect,
as is still found in some power IC processes) the ballast can
be a handy crossunder and cost you little in terms of net
area.