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Hi raghu_eee,
The total noise in the ADC should be less than 1/2 lsb of the system. The kT/C is one of the noise sources in the ADC. Apart from this the noise from the comparator then the switching noise etc will add up to give the net noise. So while designing we first make a budget for the various noise sources and design accordingly. From kT/C noise, we will get the minimum capacitor we need to use for the cap dac used in SAR ADCs. This is often overshadowed by the requirements for matching. So the minimum size required to get a paricular resolution overshadows the min size from kT/C noise point of view.
hope this helps
how to do noise budgeting. Apart from kt/c noise, which other noise contributions i need to consider. how to take switching noise into consideration?
Also From the calculations of KT/C, i get the impression that only till 10 bit does the matching consideration overshadow the kt/c, when the resolution is more kt/c overshadows the matching, I found for 12 bit, cap value needs to be 0.1pF. Is this correct?
apart from the kT/C noise from the DAC, there will be noise contribution from the comparator. And there is the noise coming from the bandgap. The switching noise you cannot take into actual calculation. But you need to keep this in mind while setting the max noise from other sources. For switching noise, you need to carefully seperate the supply lines od analog and the digital. If possible have seperate pins for analog and digital supplies. Also putting guard rings around both the analog and digital circuitries will help in reducing the switching noise getting coupled to the analog section through the substrate.
Back to kT/C noise and matching. I guess for resolutions less than 10 bits the matching criteria is not that stringent and hence I think the design is mainly from the kT/C noise point of view. As we go higher in resolution my belief is that the matching will be the dominant criteria compared to kT/C. But it all depends on what the process is ( matching) and what sort of SNR are you looking for (kT/C).
If the full scale voltage is 1V, resolution for 10 bit and 12 bit becomes 0.97mV and 0.24mV approximately.
Sqrt (KT/C) < 1/2 *LSB implies that C has to be greater than 17fF for 10 bit and 0.28pF for 12 bit. Hence I believe that matching will overshadow KT/C for lower resolution. Please comment on this Fred.
hi raghu,
what will be the size of the capacitors from matching point of view in say 12 bits? I think you can find this in the process user guide.
this will be greater as compared to the value obtained by kT/C. Hence matching will be the criteria to look for in high resolution ADC design.
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