Keysight ADS ground connection in schematic not reflected in layout

I'm trying to simulate a microstrip stub matching network with short-circuited stub in Keysight ADS.

In the schematic, I use the MLIN component for transmission lines, MTEE for the junction, and MLSC for the short-circuit stub (I also tried a combination of an MLIN + ground instead but the result is the same). When I simulate s-parameters, results are as expected (I get s11 = s22 = -1 and s12 = s21 = 0 at DC).

However, when I automatically generate a layout from the schematic, I don't get the same behavior, instead I get the behavior that the circuit would have with an open-circuit stub. For example, I get s11 = s22 = 0 and s12 = s21 = 1 at DC. To confirm, I replaced the components with MLOC and got the same result, so it seems that the ground connection is not being modeled.

How do I tell the layout tool that I want the stub to be connected to ground in the layout? I would rather not complicate the layout by adding ground vias, etc. Just instruct the simulator to treat the end of the stub as ideally connected to ground.

You have to use VIAs, no way out.Is there any other possibility to connect a Stub to GND in reality ?? No..
So, VIAs are necessary..In order to simulate you layout only, you can place a Port to the point to be tied to GND then you can simulate your layout in schematic co-simulation environment and you connect that Port to GND .. It's also possible but it doesn't represent the reality..

Thanks for the hint to add ports at the point to be grounded. So I added those ports, then defined a very small port impedance there (near 0 ohm, can't put exactly 0 ohm). And now my s11 and s21 look as expected.

Really wish the layout tool would understand that if a point is connected with a ground symbol at the schematic, it should have a port with 0 impedance there.

henrickdavis said:

I would rather not complicate the layout by adding ground vias, etc. Just instruct the simulator to treat the end of the stub as ideally connected to ground.

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I cannot recommend to do that, because you EM simulate something that you can't build. The MLSC mode automatically creates a "2D sheet" via at the end of the MLSC. If that connection is missing in your result, you forgot to map that layer (default: "hole") as a via in the Momentum stackup.

henrickdavis said:

Really wish the layout tool would understand that if a point is connected with a ground symbol at the schematic, it should have a port with 0 impedance there.

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I disagree. Momentum is meant to provide a physical result that is based on the actual layout, and should not introduce ideal connection from schematic.
When used properly, Momentum will include the short. You just missed to include the via layer ("hole") in your Momentum stackup.

volker@muehlhaus said:

I cannot recommend to do that, because you EM simulate something that you can't build. The MLSC mode automatically creates a "2D sheet" via at the end of the MLSC. If that connection is missing in your result, you forgot to map that layer (default: "hole") as a via in the Momentum stackup.



I disagree. Momentum is meant to provide a physical result that is based on the actual layout, and should not introduce ideal connection from schematic.
When used properly, Momentum will include the short. You just missed to include the via layer ("hole") in your Momentum stackup.

View attachment 156517

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Ok thanks for providing the correct way to do it.

Hello volker，could you explain what the “2D sheet via” mean？How does the simulator calculate the resistor of the via，that is a line in the layout window？

Besides，I have one more question. When I EM simulate the interconnect of the transistors (metal stacks and vias) to capture the parasitic parameters at 200 GHz，where should I set the port’s ground reference？（From the help manuel for Momentum，the distance between ±pins of one port should be electrically small，so global ground is too remote(~300um below) to use.）

fatbee said:

Hello volker，could you explain what the “2D sheet via” mean？How does the simulator calculate the resistor of the via，that is a line in the layout window？

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The 2D sheet is what 2D implies, a sheet instead of a volume. In EM simulators we can have infinitely thin sheets with thickness for resistance determined from skin depth or user input. But for this 2D sheet via case, I don't know what thickness would be used. It might not matter much ... the most relevant effect here is inductance of that via sheet. For more realistic results, I would include a circular via in layout and simulate that.

fatbee said:

When I EM simulate the interconnect of the transistors (metal stacks and vias) to capture the parasitic parameters at 200 GHz，where should I set the port’s ground reference？（From the help manuel for Momentum，the distance between ±pins of one port should be electrically small，so global ground is too remote(~300um below) to use.）

Click to expand...

There is no trivial answer, multiple things to consider. I would use global ground at the bottom of the substrate, if there is no common M1 ground available. Despite the warning, we re-wire EM results at schematic level so that all current will only flow through the actual conncetions. By having a global ground (same for all ports) we enable all modes, whereas explicit ground pins would for enforce a specific mode and might block other modes (in simulation) that might exist in real hardware.

But please take my advice with a grain of salt, most of my Momentum work is below 100 GHz and I haven't pushed port ground distance to the limits, so I don't know when the math really breaks.

Thanks for your kind reply.

When the result contains “un-physical behavior” warning，do I need to eliminate it by adjusting some settings？
Thank you.

fatbee said:

When the result contains “un-physical behavior” warning，do I need to eliminate it by adjusting some settings？

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There are no magic settings to eliminate that.

Note the message says "The distance between the layout pins for port 1 is electrically large above xxx GHz, S-parameters may become unphysical." This is based on geometry, not actual results. And that warning refers to the single ended excitation where the actual circuit port is at that ground, which implies a theoretical problem: ports must never be large because we can't interpret that. But as I wrote, we re-wire things in schematic so that the effective total current to that global ground is zero, so it can be perfectly file to ignore that warning. But no warranties, you need to check carefully and use common sense in evaluating results.

There is no simple answer. If you can avoid the "large" ports, by using a common physical reference conductor at smaller distance, that is preferred. But it's not always possible.