cmyang
Newbie level 2
I'm designing a number exchange module, and so far I've been able to make it display on Seven Segment Display (S-S-D), like if I press 0 it shows 0... etc. I'm using 2 sets of 4-bits S-S-D (Common Anode).
Now I want to do like:
default states :
Now if I press 1 :
If I press 2 :
etc.
Whichever key I press, the display will not erase the already displaying number, it will shift it to the left...
And when all 8 S-S-D is full of displaying numbers like:
, at this moment, when I press a key enter a number,
like 1 it should be like :
; it should keep shifting to the left.
Here's my attempted code, and only been able to display it on S-S-D, and display all S-S-D
... still not able to do what's been describe above...
Now I want to do like:
default states :
Code:
0000_0000
Code:
0000_0001
Code:
0000_0012
Whichever key I press, the display will not erase the already displaying number, it will shift it to the left...
And when all 8 S-S-D is full of displaying numbers like:
Code:
486C_8763
like 1 it should be like :
Code:
86C8_7631
Here's my attempted code, and only been able to display it on S-S-D, and display all S-S-D
Code:
0000_0000
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 module keydata (clk,scano,keyin,keyout,SegOut); input clk; reg dclk; output reg [3:0]keyout=4'b1110; input [3:0]keyin; output reg [7:0]SegOut; output reg [7:0]scano; integer z1=0,zz=0; reg [7:0]bcdz; reg [2:0]scan; reg [25:0]clkin=0; reg clkindown; reg state; reg [7:0]bcdz_t; always@(posedge clk) begin clkin<=clkin+1; clkindown<=clkin[22]; end always@(posedge clkindown) begin scan<=scan+1; end always@(posedge clk) begin //--------------------- if(z1==50000) begin z1<=0; keyout<={keyout[2:0],keyout[3]};//1110->1101->1011->0111->1110(loop) end else z1<=z1+1; //--------------------- //--------------------- if(zz==10000) begin zz<=0; dclk<=~dclk; end else zz<=zz+1; //--------------------- end always@(posedge clkindown) begin case(scan) 0: scano<=8'b1111_1110; 1: scano<=8'b1111_1101; 2: scano<=8'b1111_1011; 3: scano<=8'b1111_0111; 4: scano<=8'b1110_1111; 5: scano<=8'b1101_1111; 6: scano<=8'b1011_1111; 7: scano<=8'b0111_1111; default: scano<=8'hFF; endcase end always@(posedge dclk) begin if (keyout==4'b1110) begin if(keyin==4'b0111) begin bcdz<=4'b1100;//C end else if(keyin==4'b1011) begin bcdz<=4'b1101; //D end else if(keyin==4'b1101) begin bcdz<=4'b1110; //E end else if(keyin==4'b1110) begin bcdz<=4'b1111;//F end end else if (keyout==4'b1101) begin if(keyin==4'b0111) begin bcdz<=4'b1000; //8 end else if(keyin==4'b1011) begin bcdz<=4'b1001; //9 end else if(keyin==4'b1101) begin bcdz<=4'b1010; //A end else if(keyin==4'b1110) begin bcdz<=4'b1011; //B end end else if (keyout==4'b1011) begin if(keyin==4'b0111) begin bcdz<=4'b0100; //4 end else if(keyin==4'b1011) begin bcdz<=4'b0101; //5 end else if(keyin==4'b1101) begin bcdz<=4'b0110; //6 end else if(keyin==4'b1110) begin bcdz<=4'b0111; //7 end end else if (keyout==4'b0111) begin if(keyin==4'b0111) begin bcdz<=4'b0000; //0 end else if(keyin==4'b1011) begin bcdz<=4'b0001; //1 end else if(keyin==4'b1101) begin bcdz<=4'b0010; //2 end else if(keyin==4'b1110) begin bcdz<=4'b0011; //3 end end end always@(bcdz or state) begin case(bcdz) 0 : case(state) 0 :begin SegOut <= 8'hC0; state <= 1; end 1 : SegOut <= 8'hC0; endcase 1 : case(state) 0 :begin SegOut <= 8'hF9; state <= 1; end 1 : SegOut <= 8'hF9; endcase 2 : case(state) 0 :begin SegOut <= 8'hA4; state <= 1; end 1 : SegOut <= 8'hA4; endcase 3 : case(state) 0 :begin SegOut <= 8'hB0; state <= 1; end 1 : SegOut <= 8'hB0; endcase 4 : case(state) 0 :begin SegOut <= 8'h99; state <= 1; end 1: SegOut <= 8'h99; endcase 5 : case(state) 0 :begin SegOut <= 8'h92; state <= 1; end 1: SegOut <= 8'h92; endcase 6 : case(state) 0 :begin SegOut <= 8'h82; state <= 1; end 1: SegOut <= 8'h82; endcase 7 : case(state) 0 :begin SegOut <= 8'hF8; state <= 1; end 1: SegOut <= 8'hF8; endcase 8 : case(state) 0 :begin SegOut <= 8'h80; state <= 1; end 1: SegOut <= 8'h80; endcase 9 : case(state) 0 :begin SegOut <= 8'h98; state <= 1; end 1: SegOut <= 8'h98; endcase 10 : case(state) 0 :begin SegOut <= 8'h88; state <= 1; end 1: SegOut <= 8'h88; endcase 11 : case(state) 0 :begin SegOut <= 8'h83; state <= 1; end 1: SegOut <= 8'h83; endcase 12 : case(state) 0 :begin SegOut <= 8'hC6; state <= 1; end 1: SegOut <= 8'hC6; endcase 13 : case(state) 0 :begin SegOut <= 8'hA1; state <= 1; end 1: SegOut <= 8'hA1; endcase 14 : case(state) 0 :begin SegOut <= 8'h86; state <= 1; end 1: SegOut <= 8'h86; endcase 15 : case(state) 0 :begin SegOut <= 8'h8E; state <= 1; end 1: SegOut <= 8'h8E; endcase default : SegOut <= 8'hFF; endcase end endmodule