Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

just need a clarification on setup time fixing

Status
Not open for further replies.

sp3

Member level 5
Member level 5
Joined
Jan 1, 2008
Messages
82
Helped
13
Reputation
26
Reaction score
10
Trophy points
1,288
Activity points
1,848
doubt on timing

Hi all,

just need a clarification on setup time fixing.

Is it possible to fix the setup time violation by adding delay buffers on the clock path (so that data gets enough time to arrive at the capturing FF). ??

Thanks,
sp3
 

Re: doubt on timing

It can fix the setup time but it will introduce some undesirable clock skew affecting the timing of the next stage.
 

    sp3

    Points: 2
    Helpful Answer Positive Rating
doubt on timing

Hello Friend,

Yes it can fix the setup viol. But it is not always preferable as mentioned by our member, useless_skew.

Focus mainly on the minimizing the combo delay in that path. Minimizing the combo delay can be by
1. modifyng the logic without effecting the functionality.
2. Upsize/Down sizing the cells in that path.
3. Optimal fanout by replicating the logic..

But yes, until the adding buffers in the clock path (increasing the skew) doesnt effect the timing in any other stages, you can add buffers.

Hope this answers to your question.

Regards,
Sunil Budumuru
 

    sp3

    Points: 2
    Helpful Answer Positive Rating
Re: doubt on timing

Thanks a lot for your replies :)

sp3
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top