JTAG

[WannabeEngineer]

Hi, I want to insert JTAG for boundary scan and Scan chain for ATPG. For boundary scan, I am using the JTAG Pins and for scan I want to use TDI and TDO as scan in, scan out including shift_enable and testmode_scan test signal.
1) Can I use TDI TDO as scan in scan out? How do I ensure that for atpg and bsv, TDI and TDO pin working as intended?
2) Do I need a separate testmode for boundary scan?

 

[glennramalho]

Boundary scan and ATPG scan are quite different tests, they have nothing in common on how they work, when they are used or which are their objectives, so I would keep them as completely separate modes.

As for sharing pins, it depends on your DFT strategy. For the boundary scan, all commands and pins are already predefined. The only thing you want to make sure is your chip is not doing something funny during the test. Keep in mind that who will be doing the boundary scan is the PCB manufacturer, so he is going to get a lot of chips together on the PCB, get the BSDL files, run the test, perhaps program some on-board memory and use the long chains for that. So there is no "testmode" sequence, just the boundary scan commands to run. So if you need some boundary test mode signal, that depends on your design. This way your BSV will not be affected at all by the ATPG scan.

For ATPG test, we are in the test house, so there is no PCB yet. We can be doing this at wafer level or a packaged device in the tray. The usual practice is to have a single pin, let's call it scanmode to avoid confusion. It is usually a single pad which, when high, it will make some changes on the chip. Perhaps it will bypass resets, perhaps it will bypass some PLL, it probably switches some MUXes on pins. So in this case you are free to share all JTAG pins with scan pins, so yes, you could use TDI and TDO as scan in and scan out, TCK as scan clock, and maybe TMS as scan enable.

The tool manuals will stress that scanmode should be a separate pad with no sharing at all. This makes life easier, the tools expect it, so it is best that way. Now, can you share it, well, I have seen it, but it there is some delicate work there.

• you said you wanted to control the ATPG scan via the JTAG controller, you would, of course, need a jtag controller and make sure it is not in the scan chain, as there won't be a controller when the chains are activated.
• also keep in mind that, traditionaly the tester powers up the chip in scan mode (with scanmode pin high) or in functional mode (with scanmode low). If scanmode is a JTAG command it will power up in functional mode, so the chip could go of doing some nonsense and then go to scan mode when you finish issuing the command. So is that safe for your design? Your test flow? Perhaps it is ok if your functional clock is external (no internal oscillators) and then your chip won't do anything, and the tester can calmly give the sequence to enter scanmode and then wait enough time for the signal to propagate throughout the chip.
• as for sharing scan enable it could be messy as the tester is constantly taking that pin up or down. So it could be a bottle neck. I would think that could be a problem. Plus I do not know if the tool will handle it right (I never tried it), I wonder if you would have to hack the STIL files by hand. Best is probably to simply pick some unrelated functional pin and declare it to be scan enable in scanmode
• Often you see people putting other scan related signals in JTAG commands, like scan compress (EDT) enable, perhaps OPCG enable, OPCG programming, and so on. But be careful there.

 

[WannabeEngineer]

I apologize, My question was a bit unclear. My intention is use only JTAG TDI, TDO pin to use as shared pin as SCAN IN and SCAN OUT. In this case, scan_mux is controlled by a testmode pin. When testmode is high, the TDI, TDO can act as SCAN_IN, SCAN_OUT. From my understanding, any tests other than ATPG, the testmode will be low. So, for boundary scan or JTAG instructions the testmode pin will be low. Now, for boundary scan operation, I need the boundary scan cells to be enabled. For this enablement, I need a control signal. That's where my question comes, Can I use the same testmode pin? or Do I need a separate testmode?

 

[glennramalho]

Ok. No, you don't need a boundary test enable pin. The on-chip tap controller will handle that. When the PCB has been assembled, all chips with JTAG will be on a chain. Then, the PCB tester will use the JTAG commands EXTEST, PRELOAD, and SAMPLE to run the boundary test. Inside the chip, your tap controller should detect the command and raise an enable signal that tells the boundary cells to go to boundary test mode.

 

[KlausST]

Hi,

do you want to build the built-in boundary scan test? --> then you need to use all the JTAG lines and use the JTAG commands as already explained.
or do you want to code your own test? --> then you are free to use any pin and write oyur own commands.

Klaus