[SOLVED] JTAG TCK Speed Restriction

[IanTrout]

Hi Everybody,

This is my first post on this forum, and I have a small question regarding JTAG...
The internal clock (TCK) of JTAG systems is restricted to several MHz, why is that?
Where's the bottle neck on the system? Has this bottle neck been addressed in the newer models of the standard (the IEEE 1149.7, or other draft standardizations)?

Ohh, and regarding the location of this post, I didn't know where to post it, so if one of the moderators has a better place for it, please just let me know for future reference...

Thanks in advance,
IanTrout

 

[ckim]

Hi Everybody,

This is my first post on this forum, and I have a small question regarding JTAG...
The internal clock (TCK) of JTAG systems is restricted to several MHz, why is that?
Where's the bottle neck on the system? Has this bottle neck been addressed in the newer models of the standard (the IEEE 1149.7, or other draft standardizations)?

Ohh, and regarding the location of this post, I didn't know where to post it, so if one of the moderators has a better place for it, please just let me know for future reference...

Thanks in advance,
IanTrout

Ian,
There isnt a limitation on TCK in the 1149.1 standard itself. Like any synchronous data transmission there is a limit as to how much effort will be put into the IC design. Most devices top out at 50 or 60Mhz. This is fairly reasonable throughput for a full duplex ( 50mbits/sec of data going in two directions) protocol that is LVTTL based.
High speed links such as PCIe are based on LVDS, low voltage differential signaling. 1149.7 only advantage is the use of two pins, but this ends up being slower since it is half-duplex and has latency to turn the data stream around.
The other limit is due to routing TCK/TMS at the board level. Driving TCK/TMS with many end-points (inputs to each chip) over cable can limit frequency. A Scan Ring linker can give you more point-to-point routing and re-timing of the JTAG signals relative to TCK.
Hope it helps.
Cindy

 

[treqer]

xilinx edk 750khz 1500khz .........24Mhz

 

[ckim]

xilinx edk 750khz 1500khz .........24Mhz

To be clear, those are limitations of the Xilinx USB pod and not a limitation of all commercial JTAG pods nor the standard itself. Please note also that USB 2.0 is half-duplex and JTAG is full-duplex. Hence there is a lot of data transfer inefficiencies in USB 2.0 based pods since they must FIFO and hold the data every 256bytes or so and then turn the USB bus around.
The question was is there a TCK speed restriction in the standard and the answer to that is 'no'. There are limits in design, which brings around a 50Mhz/66mhz (some Xilinx parts) limitation.

Cindy

 

[treqer]

Oh! Can you explain why I am not running a chain of 32 units at the smallest frequency?

 

[IanTrout]

Ian,
There isnt a limitation on TCK in the 1149.1 standard itself. Like any synchronous data transmission there is a limit as to how much effort will be put into the IC design. Most devices top out at 50 or 60Mhz. This is fairly reasonable throughput for a full duplex ( 50mbits/sec of data going in two directions) protocol that is LVTTL based.
High speed links such as PCIe are based on LVDS, low voltage differential signaling. 1149.7 only advantage is the use of two pins, but this ends up being slower since it is half-duplex and has latency to turn the data stream around.
The other limit is due to routing TCK/TMS at the board level. Driving TCK/TMS with many end-points (inputs to each chip) over cable can limit frequency. A Scan Ring linker can give you more point-to-point routing and re-timing of the JTAG signals relative to TCK. Read more: JTAG linker

Hope it helps.
Cindy

Thanks!
For some reason our teacher found it really hard to explain this to us, and basically dodged the question every time