Job opportunity for Backend design Engineers for Mirafra Technologies!!

We are hiring Physical Design & STA Synthesis Lead for India (Bangalore) with 5 -10 Years of exp.

Also, we multiple onsite (Singapore/Taiwan) requirements for PD/STA engineers with minimum 3+ years experience.

Wonderful Opportunity as we are one of the fastest chip design Services Company, Awesome Work Culture, One of the Top Pay master in the industry.

Interested candidates can email me resumes to ranganayakulu@mirafra.com or share with your friends and colleagues.

1) Physical Design:

1. Should have worked on the entire PD Flow from netlist to GDS (Floorplanning, Power Planning, Placement & Optimization, CTS, Routing,ECO steps, Timing/SI)
2. Should have very good idea about OCV/MM/MC and multi power designs(Level shifters, Isolation cells etc)
3. Should have worked extensively on XTalk/SI/EM
4. Should be familiar with DSM topics like OPC/CMP etc for 65nm and lower technologies
5. Should be very strong on CTS constraints and skew fixing
6. Tool specific knowledge: Talus, ICC, SOC, depending on the background
7. Good understanding of library preparation in any environment (Synopsys,Magma or Cadence)
8. Knowledge of DRC/LVS, IR Drop, Formal Verification and Synthesis an added advantage
9. Job would require complete ownership from netlist to GDS for blocks. Should have done similar job well in the past
10. Should have worked on 65nm and lower technologies.

Tools : ICC or Talus for PnR , Encounter for FloorPlan , Redhawk for IR
Drop, PT/PTSI , Calibre Activities : Physical design of Hard
Macros/Partitions of sizes upto 1000K placeable instances from
gate-level-Netlist to GDS ,technologies varying from 45nm to 28nm . PD
activities involve , Hard Macro floorplan/IR
Drop/placement/CTS/Routing/Timing Optimization/Timing Closure/DRC/LVS
EXP :5-10 yrs .


2) STA/Synthesis
1. Should be very strong in Synthesis & Timing concepts
2. Should understand .lib very well. Should be aware of all types of libs like NLDM, CCSM, ECSM etc.
3. Should have knowledge of DC-topo of similar concepts in other tools (RTL Compiler, talus)
4. Timing basics should be very strong
5. Should understand the clocking structures and concepts very well.
6. Should have handled both block and top level. Should know the concepts of budgeting other techniques to handle hierarchical designs
7. Should have done both pre and post layout STA
8. Should have basic knowledge of Formal verification, Spyglass

EXP :4 -10 yrs .


Looking forward to hear from you and Feel free to reach me for any further details ,email an updated profile with contact details to ranganayakulu@mirafra.com