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Your ZCS design is poor because it fails to use the symmetrical duty cycle of a limited sine wave to precisely produce a clock out. It is basically a precompensated half wave limiter using the asymmetry of an optocoupler threshold with far too many random parts added with no benefit and no clear design.  Hence jitter is inevitable and will change in batches due to hFE variations and LED variations.  It all starts badly due to no theory of operation or design specs. Although I don't need it, you do.

Simply make an AC limiter however you know how that produces 50.0% duty cycle then delay the signal x microseconds and compare (XOR) to produce a ZCS. 

If you need isolation or lightning suppression, use 1:1 transformer as a CM choke or choose a Balun with high L BEFORE the limiter, not after. Then expect 40~60 dB CMRR. 

 Use R or C divider to ~2Vp and only need 5V logic voltage. 

If using NPN use negative feedback with high CE gain reduced to 30 dB gain for better symmetry.  A comparator does the job.  You can even use a CD4000 style logic buffer as a linear AC amplifier with 40~60 dB gain.  Opto-transistors are much less symmetrical due to the 3:1 hFE tolerance range in gain..

There are many other simple ways to make a jitter-free precise ZCS signal.

Start with good design specs for a limiter then define where you want the ZCS pulse leading/trailing edge.