Jitter seen on mains zero cross signal?

I imagine that "before" is really "delayed almost a full cycle" and a long timing ramp to get long delay is going to transform voltage noise into time noise (random jitter) at higher "gain".

Your stated jitter band, 15us, seems like <0.1% of period, I call that not bad if my take is correct.

Your stated jitter band, 15us, seems like <0.1% of period, I call that not bad if my take is correct.

Click to expand...

Thanks, i think you are right...the original thought train was that the jitter was somehow coming from mains noise...though as i think you would agree, this is unlikely...its more of a scope artefact.

The thing is, why is the jittering not seen with the circuit where the rising edge of the zero cross pulse comes "just after" the zero cross?....or, is that what you were saying about the "just before" one actually being delayed almost a full cycle, and the "long delay"?

dick_freebird said:

I imagine that "before" is really "delayed almost a full cycle"

Click to expand...

It isn't. The circuit is partly high-pass filtering mains voltage to achieve negative phase shift. Unfortunately this amplifies harmonics and switching noise.

The circuit design approach seems a bit arbitrary to me.

Thanks i see your point, though the first bit of the filer is a low pass 10k/10n RC filter, i am surprised this isnt able to slug out the noise (if it is noise and not scope jitter).

You could check with a band filter that let pass only fundamental wave.

DavedohEEG did not test the trigger threshold on AC coupling for an offset error but there seems to be interference from a 200 kHz LO reference in the sweep PLL.
Nor did he try Trigger View if avail.

Your ZCS design is poor because it fails to use the symmetrical duty cycle of a limited sine wave to precisely produce a clock out. It is basically a precompensated half wave limiter using the asymmetry of an optocoupler threshold with far too many random parts added with no benefit and no clear design. Hence jitter is inevitable and will change in batches due to hFE variations and LED variations. It all starts badly due to no theory of operation or design specs. Although I don't need it, you do.

Simply make an AC limiter however you know how that produces 50.0% duty cycle then delay the signal x microseconds and compare (XOR) to produce a ZCS.
If you need isolation or lightning suppression, use 1:1 transformer as a CM choke or choose a Balun with high L BEFORE the limiter, not after. Then expect 40~60 dB CMRR.
Use R or C divider to ~2Vp and only need 5V logic voltage.
If using NPN use negative feedback with high CE gain reduced to 30 dB gain for better symmetry. A comparator does the job. You can even use a CD4000 style logic buffer as a linear AC amplifier with 40~60 dB gain. Opto-transistors are much less symmetrical due to the 3:1 hFE tolerance range in gain..

There are many other simple ways to make a jitter-free precise ZCS signal.
Start with good design specs for a limiter then define where you want the ZCS pulse leading/trailing edge.