Jitter problem in PLL

[Vitamin-C]

pll layout jitter

Hi, All,

I have jitter problem with a PLL circuit. In my design, there is a bandgap circuit which generates references to a regulator and also the voltage to control the centre voltage for the VCO (differential ring oscillator).

The jitter is as high as 0.20UI. My problem is that when the regulator output is loaded with a capacitor and resistor (in parallel) the jitter is
greatly improved to 0.05UI. I don't know what causes this problem,
will anyone have any idea ?

Thanks in advance,
Vita

 

[atmaca]

To say anything without seeing the circuit is difficult.
If you post schematic of your circuit, may be, I can help you.

Thanks,[/url]

 

[gold_kiss]

Hi,
I had similar problem ...thats jitter in PLL. But my circuit didnt make use of BandGap, instead it used Vdd_a.

Now, the problem in my circuit was that jitter was due to power supply noise.

And your case the jitter is due to loading. Well sounds interesting.

Lets see, can you brief more on your circuit details, topology of delay elements ? supply voltage? inter node capacitance?

But its difficult to figure this one.
Cheers,
Gold_kiss

 

[Vitamin-C]

I have to re-state the question, coz I made a mistake.
the loading should be the bandgap output instead of regulator

I have jitter problem with a PLL circuit. In my design, there is a bandgap circuit which generates references to a regulator and also the voltage to control the centre voltage for the VCO (differential ring oscillator).

The jitter is as high as 0.20UI. My problem is that when the bandgap
output is loaded with a capacitor and resistor (in parallel) the jitter is
greatly improved to 0.05UI. I don't know what causes this problem,
will anyone have any idea ?

Thanks in advance,

 

[atmaca]

What happens, If you put the resistor and does not put the capacitor ?

I guess the capacitor does not have any effect.

The resisitor helps some mos transistors (if you used) to be in saturation region.

As I said, if you send the circuit diagram, may be, I can help you.


Thanks

 

[Btrend]

there are two possibilities:
1. the driving capability of bandgap is not enough, which make it
a "high impedance" point, so if any noise couple to it, it will not be able
to reduce it.
2. the phase margin of your bandgap control loop is not enoguh

 

[hermes88]

regulator has very slow response time (typical bandwidth is 1MHz) and vcc noise can only be removed by capacitor from vcc to groung, the regulator just charge the cap
you may want to have several cap from ~pf to ~uF to cover different noise range

 

[sutapanaki]

you said your bandgap controls the center frequency of the VCO. Did you check the voltage at the output of the bandgap in time domain with and without the capacitor. If it is noisy without the cap this will cause jitter.