Jitter in PLL caused by supply noise

[gold_kiss]

Hi,
Can anyone help me on this.

I have a PLL design, where the VCO ring oscillator is Current Starved.

Well the main problem faced is jitter caused by supply noise.

I have read few papers on minimizing the jitter caused by supply variations, using reference voltage generator and use of replica bias circuitry.

Now these papers include replica bias, but the delay cell are differential delay elements with symmetrical loads.

In my case I have simple current starved elements. How can I incorporate Replica bias in such configuration ?

Any help can be highly appreciated.
Cheers,
Gold_kiss

 

[rfsystem]

Re: Jitter in PLL

Use for the ring oscillator a separate supply. Place a decoupling cap on these supply which is about 5-20x the gate cap in this ring oscillator. The operating speed or frequency for your ring oscillator is then about linear with this supply starting from the sum of the two threshold voltages. Use a long channel PMOS 4-10x Lmin as a current source to drive the ring oscillator supply. The supply voltage reaches a steady state if the current drawn by the ring oscillator equals the injected. So now the PMOS gate is your VCO input. This arrangement gives the best supply rejection possible. To isolate substrate use differentially or interleaving of two odd oscillators. Then substrate noise is a comon mode which has some rejection. For reducing substrate noise gradients use classic analog layout techniques. The output to normal supply logic should be via translators. Two inverted NMOS plus crosscouples PMOS.

Please post your results. Share your experience also with other users and do not take only and disappear.

 

[gold_kiss]

Re: Jitter in PLL

Hi rfsystem,
I appreciate your response.

But please remember I am not starting a fresh PLL (VCO) design. I need to find solution for power supply variations.

I am using Current starved ring oscillator. I am biasing the pmos arm using current mirror. The pmos arm is nothing else but current source.

Do I need to account for replica bias in my circuit and if this is for sure then how do I design this replica bias?

Thanks again,
Gold_kiss

 

[rfsystem]

Re: Jitter in PLL

Hi gold_kiss,

the replicate bias gives some rejection for low frequency effects but the issue or drawback of your circuit is that the current sources are driving individual nodes. The high frequency noise injector is the bulk-drain diode of yours PMOS individula node current source. Because of the high frequency operation of that node the node cap is also low. Therefore the high frequency rejection is very limited. That is addressed by the former circuit proposal. If you have to debug your circuit on metal level you could high frequency isolate the bulk. Connect the bulk through a RC filter to VDD. That causes some vertical PNP action if you switch on VDD but with some substrate contacts it is acceptable. Otherwise you have to use a separate regulated supply for the PMOS sources.

 

[nuderen]

Jitter in PLL

It seems very difficult to realize



Useless post. Warning.
/pisoiu

 

[uncle_urfi]

Re: Jitter in PLL

Add inductors in series with the PMOS bias transistors. this will minimize the noise injection from the supply by about 4dB. and use a separate supply for the ring derived as follows.


vdd =========\\\\\\\====vddring======


where \\\\\\ is an inductor

Also attach a decoupling cap to the vddring.

 

[andy2000a]

Re: Jitter in PLL

another reduce PLL jitter

1. modify IO PAD -> PLL output have large jitter cause by I/O cell
maybe ESD or IO_pad no power_cut ..

2. reduce VCO charge pump current -> charge pump current step
small will reduce jitter ..

3. VCO VCTR use shield



But I have another question on VCO cell
If I want to design a 4-stage differential VCO cell and
get 8 phase waveform .. for Data recovery circuit
I let all node have the same Cap loading ..
but real chip still have phase error ..

why ??

how to reduce VCO cell phase ??

 

[tlihu]

Re: Jitter in PLL

another reduce PLL jitter

1. modify IO PAD -> PLL output have large jitter cause by I/O cell
maybe ESD or IO_pad no power_cut ..

2. reduce VCO charge pump current -> charge pump current step
small will reduce jitter ..

3. VCO VCTR use shield



But I have another question on VCO cell
If I want to design a 4-stage differential VCO cell and
get 8 phase waveform .. for Data recovery circuit
I let all node have the same Cap loading ..
but real chip still have phase error ..

why ??

how to reduce VCO cell phase ??

Most likely the phase errors come from physical layer, say, mismatches, wiring, etc. Just like opamp does have offsets.

 

[gold_kiss]

Re: Jitter in PLL

Hi Guys,
I appreciate your replies. Well, let me now share my bit of experience over here. We (PLL design team) have come-up with few novel solutions in particularly to reduce the jitter caused by supply noise.

What delay elements that we use in the VCO are basically differential delay elements with symtrical loads ...some thing similar proposed by Jon Meantis....papers.

Now, we studied lots of options ...IEEE JSSC etc ...and finally decided on Replica bias circuitry.

So we have something like

Jitter rejection circuiutry ----> Op amp (high unity gain)----> half delay cell ---->to supply rails of VCO.

Jitter rejection circuitry is simple Resitor divider n/w.

Op amp ....one needs to actually work on deriving its spec....probably if anyone is really interested I can post it next.

The Opamp is basically an error amplifier ...i.e a f/b circuitry.


Simulation results can also be available.

Cheers,
Gold_kiss

 

[eric1341]

Re: Jitter in PLL

Hi Gold_kiss
Could you more explain your Replica bias?
Any special request for this OP?
I am also face a little problem. It seem can't take too large of Vsw...
and if PMOS laod with big W/L, the Vsw will be smaller and dampling when at low frequency operation.