Jitter Calculation on a crystal Oscillator

I want to calculate jitter on the output of a XTAL buffer. The EDA tool I am currently using is CADENCE. Any ideas on how I could perform such a calculation?

I use script to measure the every period, then display in a diagram.
I think you can use eye diagram, but i never try it.

Because the crystal oscillator has very high-Q property, it is not easy to see the jitter from crystal oscillator. The accuracy of simulator must be very small. If not, I think you will measure the jitter from simulator not circuit itself. It is a very diffucult problem.

Yibin.

i think u need some kind of spectrum analyzer from HP or some other equipment.crystal osc's are usually low-jiter and used to generate master clocks.

regards
amarnath

amarnath said:

i think u need some kind of spectrum analyzer from HP or some other equipment.crystal osc's are usually low-jiter and used to generate master clocks.

regards
amarnath

Click to expand...

crystal osc. itself have very, very low gitter and more depend of connected
desision-depend circurits ie smith-triggers and comparator to make squarewave
from sinus-wave, this circurit have always small uncertain window to desire
between 'low' and 'High' from sinus and infuence from termic noise, PMRR, surrounding noises from other circurits and lead or lag outputs decise point between low and high and intruduce gitter.


If you using PLL, you have locked, free running - wideband ocillator (low Q compare to crystall) with servoloop (PLL) adjusting to correct frequency - but hard to make low gitter same as crystal depend of low-Q element (exor input in PLL)
and oscillator itself sucking up sourronding noises and disturbance ie lack of very
high-Q band pass filters in circurits....


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you need very good - high dynamic spectrum analyser with very good
oscillator inside to measure this - and more or less meaningless to simulate it depend so many big physical parameters outside datamodels, influens on result
(circurit boards design, PSU, MCU work depend of firmware and select of algorithm etc. etc)

you need also many hour of practical exprimenting on prototyp if want very low gitter and all surrounding equipment from PSU to board layout and screenings influece on result.

don't foget make space to LP-filter of _all_ traces from PLL/oscillator to other circurits and PS - CPU:s data-trace for program PLL-circurits for example, transporting very much noise from CPU and make gitter on PLL

I'm more or less sure you not have simulator models for this situation...