Re: JFET 2n4393
You didn't mention the intended resistance and voltage range and didn't specify your linearity requirements, e.g. in terms of acceptable intermodulation.
Generally, the transistor capacitances are the most serious restriction of resistive behaviour. Also the linearization circuit is working as a compensated RC divider in this frequency range. The two transistor capacitances can be expected to match by the symmetric chip design. But also the external circuit capacitances should be symmetric for Cgd versus Cgs.
A better high frequency behaviour could be possibly achieved with lower capacitance FETs. However there's basically a tradeoff between low capacitance and low Rds,on. For higher frequencies, pin-diode variable attenuators or gilbert-cell multipliers are preferable, I think.