Everything runs from the system clock, but there are combinatorial blocks between registers. So for instance, I have part of the data stored at the front of a fifo being read by an always_comb block that computes where the data wants to go. This is read by another synchronous block which will send the data.
The combinatorial feedback path I have is the following, which is an arbitration module.
| Code Verilog - [expand] |
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| input logic clk,
input logic ce,
input logic reset_n,
input logic [0:N-1] i_request, // Active high Request vector
output logic [0:N-1] o_grant); // One-hot Grant vector
logic [0:N-1] l_priority; // One-hot Priority selection vector
logic [0:N-1] l_carry; // Carry-bit between arbiter slices
logic [0:N-1] l_intermediate; // Intermediate wire inside arbiter slice
// Variable priority iterative arbiter slice generation. Final slice carry loops round.
// ------------------------------------------------------------------------------------------------------------------
genvar i;
generate
for (i=0; i<N-1; i++) begin : PPE_SLICES
or gate1 (l_intermediate[i], l_carry[i], l_priority[i]);
and gate2 (o_grant[i], l_intermediate[i], i_request[i]);
and gate3 (l_carry[i+1], l_intermediate[i], ~i_request[i]);
end
or gate1 (l_intermediate[N-1], l_carry[N-1], l_priority[N-1]);
and gate2 (o_grant[N-1], l_intermediate[N-1], i_request[N-1]);
and gate3 (l_carry[0], l_intermediate[N-1], ~i_request[N-1]);
endgenerate
// Round-Robin priority generation.
// ------------------------------------------------------------------------------------------------------------------
always_ff@(posedge clk) begin
if(~reset_n) begin
l_priority[0] <= 1'b1;
l_priority[1:N-1] <= 0;
end else begin
if(ce) begin
l_priority <= |o_grant ? {o_grant[N-1], o_grant[0:N-2]} : l_priority;
end
end
end |
A simple example of a for loop I use would be
| Code Verilog - [expand] |
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| always_comb begin
for(int i=0; i<NODES; i++) begin
s_i_data_val[i] = s_i_data[i].valid;
end
end |
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Thanks pbernadi, I will get it into an FPGA, and it synthesizes fine, but ideally, I would like to get test bench results for the networks so that I can look at packet latency etc.
I actually am getting all the results I 'need', the simulation is only failing when technically, the network has all ready failed. However, I am worried this indicates a deeper problem so don't want to ignore it.
mrfibble, thanks for finding that! I have just increased my iterations, and then gone simulate>break when delta goes crazy. I will start stepping, but my computer grinds to a halt for 10 seconds after every 2 steps, so this may take some time!
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could anyone explain what the step buttons do? The user manual doesn't really elaborate much!