library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bu2 is
port(ip_re,ip_im:in std_logic_vector(3 downto 0);
sel:in bit;
op_re,op_im
ut std_logic_vector(3 downto 0));
end bu2;
architecture bu of bu2 is
signal j,k,l,m,x,y,p,q,a,b,c:std_logic_vector(3 downto 0);
component mux is
port(a,b:in std_logic_vector(3 downto 0);
sel:in bit;
y
ut std_logic_vector(3 downto 0));
end component;
component twos_complement is
port(ain:in std_logic_vector(3 downto 0);
yout
ut std_logic_vector(3 downto 0));
end component;
begin
j<=(ip_re xor p);
k<=(ip_im xor q);
l<=(x xor ip_re);
m<=(y xor ip_im);
l0:twos_complement port map(x,p);
l1:twos_complement port map(y,q);
l2:mux port map(ip_re,j,sel,x);
l3:mux port map(ip_im,k,sel,y);
l4:mux port map(x,l,sel,a);
l5:mux port map(y,m,sel,b);
l6:mux port map(a,b,sel,op_re);
l7:twos_complement port map(a,c);
l8:mux port map(b,c,sel,op_im);
end bu;