it seems that specman will double verificationer's load.

[gerade]

you have to model the design yourself. Besides, you still have to write stimuli.

it seems quite much for the guy who is doing verification.

so what is the advantage for such in language then?

 

[the_penetrator]

Actually i am using OVL (Open Verification Library). It is not a new lang. and there exist versions of the OVL for both VHDL and Verilog. It is a package for VHDL and corresponding modules for Verilog.

You get to insert these modules that implement assertion monitors in your code (checking some scenarios of operation). These modules have translate_on, _off metacomments so the synthesis tool (Syn0psys and others i think) won't synthesize the assertion monitors. I have used them and they are working OK.

Until an IEEE standard on a verification language appears, i am sceptical on learning one. Especially with so many verif. languages out there.

the_penetrator©

 

[yerics]

I think although you don't use specman, you had to write reference module and stimuli by other language or tool.

stimuli and reference module are necessary for verification.

specman only provides some kind of verification architecture and e language for verification.

 

[rx300]

You can't get away from some sort of stimuli generator, driver or whatever you call it to wiggle the inputs. So is monitor. That's the basics of a verification environment.
You can develop driver/monitor in HDL, but HVL (high-level verification language) makes it much easier. HVLs usually come with a lot of features for verification purpose. If you want to develop a nice environment that does automatic checking, random stimuli generation, functional coverage, I don't see how you can do that in current HDL.
OVL is just a simple extension to verification environment. It doesn't do much. And it can't replace testbench.
The bottom line is, if you care about the mask, verification is very important -- over 60% of your project time. If you don't care about the cost or you're just doing FPGA design, you can probably cut corners in verifcation efforts.