Verilognoob1
Newbie level 3
- Joined
- Dec 8, 2013
- Messages
- 4
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1
- Activity points
- 56
Hello:
I'm having issues trying to build this state diagram into a Verilog code on ModelSim, my Verilog skills are very weak, thus I'm struggling with it.
The Problem:
Create Verilog source code that satisfies the given State Diagram. Prove, using a testbench, that your code satisfies every possible requirement
This is the state diagram
here is my attempt
main module
and this is my testbench
and when I simulate it in ModelSim, I get unclear results, that I don't even know what I'm doing wrong... like I said, my Verilog skills are weak... I would appreciate any help, hints, ideas, and codes
Thanks in advance.
I'm having issues trying to build this state diagram into a Verilog code on ModelSim, my Verilog skills are very weak, thus I'm struggling with it.
The Problem:
Create Verilog source code that satisfies the given State Diagram. Prove, using a testbench, that your code satisfies every possible requirement
This is the state diagram
here is my attempt
main module
Code:
module HW11 (A, B, C, D, x, y, clock, reset);
output reg A, B, C, D;
input x, y, clock, reset;
reg [2:0] pstate, nstate;
always @ (posedge clock or negedge reset)
if (reset ==0) pstate <= A;
else pstate <= nstate;
always @ (pstate or x or y) begin
case (pstate)
A: if (x==0 && y==0) nstate <= A;
else if (x==0 && y==1) nstate <= B;
else if (x==1 && y==0) nstate <= C;
else nstate <= D;
B: if (x==0 && y==0) nstate <= C;
else if (x==0 && y==1) nstate <= B;
else if (x==1 && y==0) nstate <= D;
else nstate <= A;
C: if (x==0 && y==0) nstate <= D;
else if (x==0 && y==1) nstate <= B;
else if (x==1 && y==0) nstate <= C;
else nstate <= A;
D: if (x==0 && y==0) nstate <= B;
else if (x==0 && y==1) nstate <= A;
else if (x==1 && y==0) nstate <= C;
else nstate <= D;
endcase
end
endmoduleand this is my testbench
Code:
module HW11_testbench;
wire A, B, C, D;
reg x, y, clock, reset;
HW11 I1 (A, B, C, D, x, y, clock, reset);
always
#10 clock = ~clock;
initial
begin
//$display ("time\t clock reset x y over under");
//$monitor ("%g\t %b\t %b\t %b\t %b\t %b\t %b", $time, clock, reset, x, y);
x = 0; y=0; clock = 1; reset = 0;
#5 reset = 1;
#10 reset = 0;
#10 x =0; y=0;
#10 x =0; y=1;
#10 x =1; y=0;
#10 x =1; y=1;
#10 x =0; y=0;
#10 x =0; y=1;
#10 x =1; y=0;
#10 x =1; y=1;
end
endmoduleand when I simulate it in ModelSim, I get unclear results, that I don't even know what I'm doing wrong... like I said, my Verilog skills are weak... I would appreciate any help, hints, ideas, and codes
Thanks in advance.