The issues are not of the fix types. For that, you just first need to go through the Basics of ATPG.
Also you need to know how to do ATPG with any tool. If you understand well, than you can directly got answer of your question itself.
As issues are not limited. There are number of issues.
So best thing to do is to do exercise on tool itself.
The issues are not of the fix types. For that, you just first need to go through the Basics of ATPG.
Also you need to know how to do ATPG with any tool. If you understand well, than you can directly got answer of your question itself.
As issues are not limited. There are number of issues.
So best thing to do is to do exercise on tool itself.
Come to the point,I know the tools tetra max from synopsys and Encounter test from cadence are used to generate the patterens.
we need an inputs as libraries,scan-inserted netlist to generate the patterens using atpg tool.
As u mentioned that issues are not limited.Can you share me some issues you faced in your real projects.I know only if drc issues(like gated clock,reset issues) comes,we report to design team,apart from these if u get any issues.plz share and correct me if my understand is wrong
- - - Updated - - -
Im sorry rca,Im not geting ur point.Can u elaborate???
Generally issues are coming mostly whenever we dont that much care about DRC violations at scan insertion and also @ ATPG.
Mostly the common DRCs are : Scan Chain blockage, Clock, Data, Model issues.
Please go through the User guide of any ATPG tool. You will get better understanding.
Are you saying you're not able to perform ATPG even if your DRC is clean (basic violations) ? Or you're saying you're not able to go ahead fixing the DRC's ??
No, It is not like that. We can go ahead even DRC's not clean. Because all DRC's are not that much important.
We can perform ATPG even if DRC's not clean. It totally depends on the DRC which we got for particular design.
Hi Maulin,
That's what I'm saying too. I am trying to understand if the pattern generation issue is because of any tool settings (taking long time to complete DRC /ATPG because of buffer ) or plainly because of DRC violations ?