issues on latch design

[dayang]

Hi
How can I design such a latch, that it's input is logic high and low ( dvdd dgnd),and clock. And it's output is two voltage level.for example when input is high and clock is high the output is 1.8v, when input is low and clock is high the output is 0.6v.(vdd is 3.3v). how can I realized it using minum transisters, and is there any articles tell about it? I want to use such a latch in current steering dac to reduce the glitch.Thanks

Added after 13 minutes:

the waveform is attached

 

[nandu_r]

No simple solution

1)If you want to use precise 1.8 and .6V need to go for bandgap and then generate other buffered voltage which you can use as supply and ground for a simple invertor(to get the required swing)
2) if you dont whant exact voltage(1.8V, .6V) you can exploit the vt of the transistors, to generate those voltage .