Issues in vhdl coding...plz let me know if u r aware.....

vhdl instantiate dcm in top level

Hi friends,

I am designing Data Acquisition system, in which I need to use DCM, MUX's, latches and delay elements as my lower level modules. When I instantiate them in my top module, The system runs with system clock. In the top module I have instantiated all the lower modules and under process I have take system clock as my event and portmapping is done under this process. But I am getting erros. When I remove the system clock, I am not getting erros. please anyone explain me whether portmapping can be allowed in process with clock...

Thanks in advance...

top module in vhdl

As far as i know.. u cannot port-map inside a process. Port-mapping is done outside the process.

It doesnt make sense to port-map inside a process. Since you are "describing" hardware, making it 'sensitive' to some clock signal doesnt make sense. The described hardware wont change according to some 'clock'.

vhdl coding

yeah you are rute, I have assigned outputs outside the process. Now it got synthesised. One more issue is I am getting error as

# ** Fatal: Integer divide (mod) by zero.
# Time: 1000040 ps Iteration: 19 Process: /top_module/u2/dcm_sp_inst/ps_delay_md_p File: C:/Xilinx/10.1/ISE/vhdl/src/unisims/unisim_VITAL.vhd
# Fatal error at C:/Xilinx/10.1/ISE/vhdl/src/unisims/unisim_VITAL.vhd line 7216
#
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.


when I run my top module in modelsim for simulation....How do I correct the delay...

cannot continue because of fatal error vhdl

I believe, you had the same error while debugging your DCM (another post of yours).
I can see a mention of "divide by zero" in the error...

Does your testbench perform any such operation ?

modelsim cannot continue because of fatal error

Hi,

I am not using any testbench. using DCM to generate clock doubling....

fatal error unisims/unisim_vital

I cant see why a divide by zero error should occur. Have you properly instantiated the DCM ? With proper feedback ? Have tried using modelsim instead of ISE simulator ?

If possible, upload your VHDL code, or gimme a link if u've already posted it.

Re: Issues in vhdl coding...plz let me know if u r aware....

Hi plz find the attached files of my code. I got those errors in Modelsim only. I am using ISE WEBPACK-10.1 and modelsim 6.1b.....

Re: Issues in vhdl coding...plz let me know if u r aware....

I went through the code. I found some issues.

1.) In buf_soc and buf_eoc.. you have made the following assignment

O <= I after D_SOC
O <= I after D_EOC

In VHDL 'after' statement is non-synthesizable. But XST gave no error. So even i was surprised. So i decided to do a behavioral simulation on those individual buffers. And i found that they do not work. Forcing the input to '1' or '0' does not change the output. So i ran a Post route simulation.. It worked but then the 100 ns delay wasn't there... Only combinational path delay. Which proves 'after' statement wasnt synthesized.

2.) I simulated the top level module. And i got no such 'divide by zero error' and i got the expected multiplied clock on signal clk6b1o.

I am using ISE version 9.1 and modelsim XE 6.2g

Re: Issues in vhdl coding...plz let me know if u r aware....

oh....is there any other alternative for after clause, can i use wait untill? I think even it is not synthesisable....At the output i am generating the pulses with so much of time period.....

Re: Issues in vhdl coding...plz let me know if u r aware....

No you cannot use 'wait', or other such delay statements either. There is no way to introduce such timed delay directly.. We have to depend on the 'clock'.
And moreover, using 6 DCM's causes jitter accumulation.

I didnt understand what you meant by "At the output i am generating the pulses with so much of time period....."

Re: Issues in vhdl coding...plz let me know if u r aware....

Hi,

I have done my complete design module. All individual blocks are working fine. But when I integrate all I am not getting desired outputs. As you mentioned in ur earlier reply that after clause is not simulated, it worked out for me. when I change my input, after certain amount of as mentioned in the code output is changing with respect to input. However not working in top module. I am here with my complete design plz go thro' and let me know where I have gone wrong. If I cant use after clause, whats the alternative for that. I need to generate the pulses of that much duration. How can I desribe delay elements in VHDL? My top module output signals are not happening...OE,SHG,ADC_CLK. ADC_CLK is my second DCM(inst--DCM2--o/p clk is twice input clk) output. I mean twice multiplied by the output of first DCM (inst--DCM6---o/p is six times input clk)output(clk1b20_inv). I am feeding my output of first DCM as input to second DCM....

find the source files and output waveform files of top module