riceman
Newbie
Hello all,
I've been struggling with this issue for a while now and I haven't found anything in my reading as to why this is happening.
I'm using cocotb (python coroutine-based verilog simulation library) with the Xcelium simulator. I have a testbench that uses a generate loop to create multiple 'chips', and each of those chips has multiple 'rails'. I'm using system verilog at the chip and tb level so I can use reals and real math. At the tb level I have an unpacked bus of output voltages representing the output voltage of each rail for each chip. At the chip level I have explicit ports for the output of each rail, but I also need that converted into an unpacked bus so I can pass the reals into a module with multiple instantiations in bus notation (using {} to assign doesn't seem to work with reals).
tb level:
chip level:
The f_vctrl real is calculated in the CONTROL block, and I have a cocotb coroutine that takes that value (f_vctrl) and puts it through a digital transfer function and assigns the output to the unpacked bus VOUT[1:0] (one coroutine for each rail).
My issue is that the rail 0 vout (VOUT[0] -> VOUT0 -> VOUT0[0] -> VSENSE0 -> VSENSE[0]) gets passed correctly but the rail 1 (and any index above 0) doesn't seem to get passed correctly. (VOUT[1] x VOUT1 -> VOUT1[0] -> VSENSE1 -> VSENSE[1])
The VOUT[1] unpacked bus gets assigned correctly by cocotb, but it doesn't seem to propagate to VOUT1. I haven't been able to find any reason that this would happen.
Thanks
I've been struggling with this issue for a while now and I haven't found anything in my reading as to why this is happening.
I'm using cocotb (python coroutine-based verilog simulation library) with the Xcelium simulator. I have a testbench that uses a generate loop to create multiple 'chips', and each of those chips has multiple 'rails'. I'm using system verilog at the chip and tb level so I can use reals and real math. At the tb level I have an unpacked bus of output voltages representing the output voltage of each rail for each chip. At the chip level I have explicit ports for the output of each rail, but I also need that converted into an unpacked bus so I can pass the reals into a module with multiple instantiations in bus notation (using {} to assign doesn't seem to work with reals).
tb level:
Code:
`define NUM_CHIPS 1
module tb_CHIP();
real VOUT0[`NUM_CHIPS-1:0];
real VOUT1[`NUM_CHIPS-1:0];
genvar i;
generate
for (i=0; i < `NUM_CHIPS; i=i+1) begin:gen_chip
CHIP chip(
// Reals
.VOUT1(VOUT1[i]),
.VOUT0(VOUT0[i]),
.VSENSE1(VOUT1[i]),
.VSENSE0(VOUT0[i]),
);
end
endgenerate
endmodulechip level:
Code:
module CHIP(
// Reals
output real VOUT1,VOUT0,
input real VSENSE1,VSENSE0,
);
real f_vctrl[1:0];
real VOUT[1:0];
real VSENSE[1:0];
assign VOUT0 = VOUT[0];
assign VOUT1 = VOUT[1];
assign VSENSE[0] = VSENSE0;
assign VSENSE[1] = VSENSE1;
CONTROL control[1:0](
.i_VSENSE(VSENSE[1:0]),
.o_VCTRL(f_vctrl[1:0]),
);
endmoduleThe f_vctrl real is calculated in the CONTROL block, and I have a cocotb coroutine that takes that value (f_vctrl) and puts it through a digital transfer function and assigns the output to the unpacked bus VOUT[1:0] (one coroutine for each rail).
My issue is that the rail 0 vout (VOUT[0] -> VOUT0 -> VOUT0[0] -> VSENSE0 -> VSENSE[0]) gets passed correctly but the rail 1 (and any index above 0) doesn't seem to get passed correctly. (VOUT[1] x VOUT1 -> VOUT1[0] -> VSENSE1 -> VSENSE[1])
The VOUT[1] unpacked bus gets assigned correctly by cocotb, but it doesn't seem to propagate to VOUT1. I haven't been able to find any reason that this would happen.
Thanks