Issue with SAR ADC design

[dirac16]

The image below is a monotonic capacitor switching SAR ADC. The positive differential input Vip is connected to Vref, and the negative differential input is connected to voltage Vn. The goal is to find out Vn/Vref. The tricky thing however about the design is the reference voltage Vref, which is not simply a stable voltage, rather the voltage across a capacitor. In other words, I have a capacitor C which is charged to some known voltage, Vref, and what I want to do is use this voltage as both the reference voltage for my ADC, and the voltage for the positive differential input Vip.

The only solution comes to my mind is to use an op amp in a unity gain configuration. For this I hook up the op amp's positive terminal to Vref and the buffered voltage Vref is then taken at the output of the amp. This solution looks power hungry since the amp needs to provide a large gain for the accurate voltage sampling. There should be yet a better and easier solution?

 

[BradtheRad]

Please clarify whether you wish to:

* duplicate the same voltage Vref?
or
* duplicate its amplitude at the opposite polarity?
or
* create a voltage equivalent to Vsupply-Vref?

 

[dirac16]

I used a simple model to illustrate the capacitor voltage. In reality the capacitor C is connected to a pmos current source. The pmos is controlled by a pulse whose duration may vary over PVT variations. Anyway the pulse duration and the pmos sizing is such that the capacitor voltage stays around 0.4V. Now I want to "duplicate" this voltage to both serve as the reference voltage Vref and the differential positive voltage Vip for the ADC.

 

[martinnl]

I assume this means that your capacitor C has a resistor or current source in parallel to discharge it. This results in Vc to ripple up and down. Which voltage do you want to use? Do you need to sample it at a certain time?

If C is much larger than the capacitors in the DAC perhaps additional buffering is not needed. And if that is the case, connecting the same voltage to VIP won't attenuate the voltage significantly.

But why do you want to use a differential structure if one of the inputs is VREF?

 

[dirac16]

Yes right, I use an nmos current source in parallel to reset the capacitor. The sampling frequency is on the order of a few MHz.

I cannot use a large integrated cap since the DAC capacitance is already large (~1pF). So I cannot connect Vc to Vip otherwise the cap voltage will be attenuated.

Note also that the voltage Vn is generated in the same way as Vip but with a different controlling signal for the pmos current source. The schematic below shows the idea. For Vn I used the lower CDAC (the total capacitance connected to the negative terminal of the comparator) to save area and power. Note that the capacitance C should be equal to CDAC to have the same charging slope for the voltage Vref and Vn.

The differential structure allows me to avoid non-ideal switching behavior of pmos transistors both at ON and OFF state transitions.

--- Updated Jul 5, 2021 ---

If you now look more carefully this is nothing but a time to digital converter. The time Tin is equivalent to the voltage Vn, and the time Tref is equivalent to the voltage Vref. With that I am able to find the ratio of Tin/Tref which is the same as Vn/Vref as long as the pmos transistors stay in saturation region during the charging period. You can see that for Vref and Vn less than one threshold voltage the time to voltage converter is linear.

So now the major problem left is to use Vref as the reference voltage for the SAR ADC. That is my problem.

 

[martinnl]

Thanks for the clarification.

Either you go with an opamp buffer, as you said. But since you can assume, I guess, that Tin < Tref why not simply modify the DAC switching scheme to do a binary search on only the C? A adc with this configuration doesn't seem like the best choice. Wouldn't the Vref on both Vref and Vp cause an error?

You output signal would be (Vref-Vn)/Vref or (Tref-Tin)/Tref. Just shorting Vp to ground would give you - Tin/Tref

 

[dirac16]

Thanks for the clarification.

Either you go with an opamp buffer, as you said. But since you can assume, I guess, that Tin < Tref why not simply modify the DAC switching scheme to do a binary search on only the C? A adc with this configuration doesn't seem like the best choice. Wouldn't the Vref on both Vref and Vp cause an error?

You output signal would be (Vref-Vn)/Vref or (Tref-Tin)/Tref. Just shorting Vp to ground would give you - Tin/Tref

Thank you. I was going to find the complement of (Vref-Vn)/Vref which is 1-(Vref-Vn)/Vref=Vn/Vref. But right I could also ground Vip and find -Vn/Vref.

Yes, right, Tin is always less than Tref. But if you're trying to use a single-ended configuration for the ADC you'd still need to connect the bottom plates to Vref. Right? So the problem still exists.