Issue with comparator design based on OpAmp

Hi,

I have used a OpAmp based comparator in one of my designs. The first file is the circuit. Second and Third are the simulation results; the plots of the comparator inputs and output.. In that, the first sub window is the output of the comparator. Second and third sub- windows are the positive and negative input of the comparator. Though I am varying the inputs to the comparator, I don't see the expected behavior. Though inputs are varying around 1V and there is a significant difference between their inputs, my output is always around 500mV. Can you pls help me out why it is behaving so?

I can't make out much of the necessary detail, but some things to check:

- Is the front end cutting off the lower mirror, such that the output
common-source device has no variation in its Vgs and is only responding
to bias generator current? Try some more-centered common-mode
point. With one input at ground the diff tail is pulled to VT(P) and
there may be no gain in the diff-pair + mirror-load assembly.

- is the "compensation cap" (comparators don't want compensation)
so large that the output simply doesn't get where it's going, within the
timescale of the analysis? Remove it or minimize it.

Why is your schematic an extremely fuzzy negative image??
Some lines and all text cannot be seen.

Did you inspect the transistor voltages and currents in the schematic? They seem to be far-off from any useful bias point.

The differential pair is effectively turned off, the current mirror seems to be fed mainly by leakage currents. Did you copy an existing design example or assembled the circuit from the scratch?

Just trivial, a comparator won't need a compensation capacitor.

Why is your schematic an extremely fuzzy negative image??
Some lines and all text cannot be seen.

Click to expand...

IC designers apparently love the Cadence look and feel. May be you're lacking the masochistic disposition? Me too.

FvM said:

IC designers apparently love the Cadence look and feel.

Click to expand...

I will pretend I am an IC designer and turn off all the lights in my neighbourhood.
Then I will move all the parts in the Cadence schematic much closer together so they can be enlarged.
Then I will make the negative image a negative of itself so it looks reasonably normal.

FvM said:

IC designers apparently love the Cadence look and feel. May be you're lacking the masochistic disposition? Me too.

Click to expand...

No. CAD directors love Cadence. The way it used to work
is, "replace your lovingly crafted and perfectly fine tool set
with our overpriced bloatware, and we'll find you a Cadence
VP slot".

I'm looking forward to no longer using it. Unaffordable for
private individuals, unresponsive when you find (say) a
deep simulator bug that prevents convergence ("oh, that's
Berkeley's problem... we'll get back to you when they get
back to us"), and the heinous license pricing ensures that
Mr. Cad Director (more likely his successor, since Mr.
Previous CAD Director is now enjoying a nice do-nothing
VP job at the Big C) will never buy enough to support
crunch time and everybody gets to squeeze through
that design bottleneck in tandem.

Note to Cadence victims wishing to post schematics
and waveform plots - use a lossless compression image
format; Cadence draws everything 1 pixel wide by
default, and JPEG will dither away detail.

Audioguru said:

... make the negative image a negative of itself so it looks reasonably normal.

Click to expand...

Very good recommendation to all Cādence' images providers in this forum. Always have done it, and so simple:

See how all the parts are spread out too far apart?
I updated my imaging software so now I cannot (or I do not know how to) increase the contrast of a faint image like that.