ISE xc2c64a, 2 output, phase.

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Hi,

No, this does not work. I have the error when compiling:
Line 33. Object clock_out of mode OUT can not be read.
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This means you can not use this "external signal" --> then just generate another internal signal. Like here tmp2
Code VHDL - [expand]
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clock_out <= tmp;
      tmp2 <= tmp;
      clock_out2 <= tmp2;



anyway, your proposal is only inverted signal probably.
Click to expand...
Clk_out2 is delayed by 1/clk.
For sure if out_clk = clk/2 then it will look like an inverted signal.
But if you use any other divider rate (this means clk_out is any lower frequency), then it will be more obvious that it is not inverted anymore: it´s shifted by 1/clk.

20ns delay its only for example, but what we will do for delay 7 or 14ns?
Click to expand...
This is a new situation. It is not clear from your previous posts.
(For your future threads: try to write all your requirements in your first post. Else the thread becomes lengthy and our answers become irrelevant.)

--> Then either use a chip with ODELAY feature or use external RC delay as already recommended.

Klaus
 

I will be very appreciated if you give precisely chip number for ordering, where I will be the success with my target.
Click to expand...
I don't know about your project requirements, so I cannot comment.
Look into all Xilinx 7 series devices and choose the one that fits you the best.

--> Then either use a chip with ODELAY feature or use external RC delay as already recommended.
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ODELAY is not available for the Xilinx part number the OP is using.
External RC, yes possible.
 

ok, I understand need to be ordered Xilinx 7 series.
I only found this one **broken link removed** , where to buying 7 series?

found another one https://www.ebay.com.au/itm/Develop...612383?hash=item5b3d02b85f:g:uHcAAOSwX61ZJGfY

but 200$, is a normal price? or possible to find something cheapest for my target?
what exactly needed for me.
1 clock input between 50-100Mhz
4 outputs, I will divide the input clock, for example, /2 /16 /24 /64
outputs must have possibility change output delay, for example, 10ns for output1, 24 ns for output 2, etc...

any recommendation. thanks.
 

Hi,

for example, 10ns for output1, 24 ns for output 2, etc...
Click to expand...
Instead of giving confusing "examples" please specify them in a technical way:

Like:
Each clock needs to be delayed in the range of ?? ns to ?? ns with a resolution of ?? ns referenced to signal ???

Klaus
 

no problem,

clock in = 50000000Hz
clock_out1 /2 = 25000000Hz, no delayed output
clock_out2 /4 = 12500000Hz, must be delayed 7ns,compare to clock_out1
Clock_out3 /10 = 5000000Hz, must be delayed 19ns, compare to clock_out1
Clock_out4 /5 = 10000000Hz, must be delayed 4ns, compare to clock_out1

I believe this absolutely clear "example"
 

Hi,

I asked exactly for the opposite: "No example"
I asked you to replace all my "??" with values.

Now an additional new information "different frequencies" (at post #25 .... this is really late!)
--> thus you need to specify which clock edge(s) you want to refer to.

Klaus
 

it's not possible to replace your "??"
1. because for me need difference delay for every output.
2. it's not a range, it's must exactly amount.
 

If the a newer FPGA family is considered for the design, not necessarily Xilinx Spartan 7, PLL phase shift may be an alternative to synchronous delay with relative high clock frequencies.

In any case you should become clear about the specification, not only nominal delay, but also delay accuracy, run-time variation required? I think the primary objective is that you understand the programmable logic design methods and device features, because you are going to implement the design.
 

Hi,

1. because for me need difference delay for every output.
Click to expand...
I wonder because "Example" suggests that you want different values. And additionalyy you used various values in the past: "4ns, 7ns, 19ns, 20ns...".
Thus it´s at least a range of 4ns ... 20ns.
Maybe next time it is not 4ns but 4ms ... we don´t know this. But you should know this.. and tell us.

2. it's not a range, it's must exactly amount.
Click to expand...
Nothing is "exact". It allways has a granularity, noise, step size, drift....
When you say "19ns", does it mean it needs to be 19.00000ns without an allowed tolerance of 1ppm? --> Impossible.
...And next time you ask for an "exact" delay of 18.99999ns?

Look into the datasheet for a "ready to buy" delay IC. It surely will specify a delay range and a delay resolution.

Klaus
 

I will happy to look in the datasheet, please give me for example chip number.
 


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