iscas 85 benchmark circuits

[designtech]

iscas 85 benchmark

Hi,

Can anyone please tell me where I can get SPICE netlists for the iscas 85 benchmark circuits ? I need them very urgently

Thanks a lot

 

[beejan]

iscas 85 benchmarks

U can generate it very easly using perl script. It is a matetr of small program in perl.
First of all u have to to make all subckt library for basic gates and use thise subcircuits to replace the basic gates in iscas circuits.

 

[dhaval4987]

is there any tool that does this? i mean conversion from verilog to spice?

---------- Post added at 03:07 ---------- Previous post was at 02:27 ----------

I also need the same spice netlists. ISCAS combinational circuits. But I dont know perl scripting. I have verilog files. but how do I get spice files?

 

[phoenixpavan]

Hi dhaval,

Please go through these threads

https://www.edaboard.com/threads/147765/

https://www.edaboard.com/threads/55860/

 

[dhaval4987]

Thanks Pavan

I read at many places that HSIM has v2s that converts verilog to spice.

I did that, but it looks like that Verilog is converted to *.spi . However I need to perfrm an STA using Synopsys Nanotime and it reads .sp file. I need flat Spice level netlist.

How do you suggest should I move further?

 

[kottu.ramu]

Re: iscas 85 benchmark

please give the spice netlist for the benchmark circuits if you get them,and plz send them to my mail id: kottu.ramu@redifffmail.com



Thanks & Regards

 

[dhaval4987]

Hey pavan...

I have gate level spice netlist and separate spice descripption. Can you guide me how to write Perl script? May be an example script?

 

[kottu.ramu]

kindly send gatelevel spicenetlist

Thanks & Regards

 

[prakaash3442]

hey ramu i vl giv u some clue as i know how v vl get that net list but my prob is that my halwa professors need circuit diagrams so can u also help me out



the site i would suggest u is WWW: ISCAS89 Sequential Benchmark Circuits

can u also kindly help me how to get circuit diagrams of them

 

[kottu.ramu]

kindly forward to me that gatelevel netlist.........how could you generated them?

 

[prakaash3442]

hai ramu gate level net list is readily available for some of the circuits directly kindly browse the site

and sending netlist is for around for all sequential is a bit difficult so kindly u browse it u vl surely get it there is no other alternative rather than to belive the net source wether they r true or not

so kind;y browse it

 

[yaksisi]

Take a look at the following website:

Perform the SPICE Simulation of ISCAS85 Benchmark Circuits for research

or you can just search on google, key word: iscas spice

 

[Oveis.Gharan]

Thanks Pavan

I read at many places that HSIM has v2s that converts verilog to spice.

I did that, but it looks like that Verilog is converted to *.spi . However I need to perfrm an STA using Synopsys Nanotime and it reads .sp file. I need flat Spice level netlist.

How do you suggest should I move further?

Dear dhaval
I convert my synthesized veriolg code into spice netlist but i have a problem.
Every Cell (subcircuit) has its own VDD and VSS net name,

.
.
.
XU9 PA n9 X1[0] VDD_dummy47 VSS_dummy48 NAND2_X1
XU8 PA n8 X1[1] VDD_dummy49 VSS_dummy50 NAND2_X1
XU7 PA n7 X1[2] VDD_dummy51 VSS_dummy52 NAND2_X1
XU6 PA n6 X1[3] VDD_dummy53 VSS_dummy54 NAND2_X1
.
.

I want all the cells VDD and VSS be connected to the global supply net.
What do you suggest?

Thanks in advance.
Oveis.

 

[dhaval4987]

Dear dhaval
I convert my synthesized veriolg code into spice netlist but i have a problem.
Every Cell (subcircuit) has its own VDD and VSS net name,

.
.
.
XU9 PA n9 X1[0] VDD_dummy47 VSS_dummy48 NAND2_X1
XU8 PA n8 X1[1] VDD_dummy49 VSS_dummy50 NAND2_X1
XU7 PA n7 X1[2] VDD_dummy51 VSS_dummy52 NAND2_X1
XU6 PA n6 X1[3] VDD_dummy53 VSS_dummy54 NAND2_X1
.
.

I want all the cells VDD and VSS be connected to the global supply net.
What do you suggest?

Thanks in advance.
Oveis.

Dear Oveis,

use some perl scripts to perform some text manipulation and replace all VDD_dummyxx with VDD and same for VSS.
unfortunately using v2s command by hsim has a con- about the supply rail names.

But running through perl script is really easy and should solve this problem.