Is VHDL capable of testing signal size?

Status
Not open for further replies.
L

legendbb

Member level 1
Joined
Nov 16, 2013
Messages
34
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Visit site
Activity points
1,516
For example:

signal A : std_logic_vector(10 DOWNTO 0)

if sizeof(A) > 10 do ...
else do ...
end if;

???

Thanks, or use such condition in Generate clause?
 
Last edited:

yes you can. Arrays have attributes:

a_big_gen : if A'legnth > 10 generate...

etc.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…