Is Verilog operator # synthesizable?

[achandra]

It has been ages since i touched verilog. Can anyone help me remember if # sign can also be synthesized? I remember its used for delay like a = #1 b where it means assign b to a after 1 ns. Is that right?

I have got an RTL code now that has the # signs used in a statement a = #1 b;

Are there any particular scenarios where it is synthesizable?

 

[master_picengineer]

Verilog operator

Delays are not synthesizable.

 

[sameem_shabbir]

Re: Verilog operator

As far as i remeber #1 means delay of 1 time unit
If ur time unit is ns then #1 will mean delay of 1ns

Anyway # is not synthesizable in any case