is total power 0.5W okay for a PLL chip?

[Robertt]

I designed a pll chip and did the post layout simulation. the result gave me 0.5W total power dissipation. The peak power can reach 1 W.

Is that too large to burn the chip after fabrication?

I have no idea. I never taped out before. Please give me some idea. Thanks a million.

The process is Ami 0.5u. and the die are is 1*1 sqr um.

Robert

 

[RFDave]

Well, National Semiconductor and Analog Devices seem to be able to do a PLL chip with about 100 mW or so. I'd think that 500 mW is a little high. You might want to think about heat sinking.....

Dave

 

[Robertt]

heat sinking? what's that?