Is too large a Vds a reliability risk?

Say I have an NFET where max Vds is specified to be 5V.

Say in my application transients result in Vds going to say 6V repeatedly.

Should I be concerned? What exactly are the risks associated with exceeding Vds specs?
I presume it is reliability related or will it result in all out functional failure?

Exceeding Vgs, Vgd limits is clear (oxide weakening and breakdown). Exceeding Vds, Vsd limits
is however not so clear to me.

Can anyone help?

Thanks,

Diarmuid

Exceeding maximum Vds may eventually generate a breakdown as in a zener or avalanche diode. This can be lethal in a bipolar transistor, all breakdown current tends to concentrate in a hot spot. FET and MOSFET devices are somewhat more forgiving, because due to their intrinsic positive resistance coefficient current tends to be uniformly distributed across all the drain-substrate junction. Even some of them are rated for operating beyond breakdown!. Anyway, no one will guarantee your design if it uses a conventionally-specified transistor. One thing you can do is adding a zener diode from drain to gate chosen so it makes the transistor conduct as soon as voltage is exceeded, if you can tolerate conduction under this condition.
But... you gave maximum Vds = 5V in your example. No common power device is rated so low. Maybe you are talking about microwave devices, i. e. MESFETS?.

Large Vds also might lead to Hot Carrier Failure.

It will surely produce undesired results

Thanks for the responses guys.

@lw1ecp: Max vds specified by the reliability guys here is 6V for a lot of the FETs. I will talk with them as to why.

@leo_o2: That thought had crossed my mind. How exactly would this occur due to excessive Vds.

Thanks,

Diarmuid

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@leo_o2: Would you agree with what is stated here:

http://www.siliconfareast.com/hotcarriers.htm

@lw1ecp: What are typical reverse breakdown voltages for a drain of a FET?

The main reason for transistor breakdown due to large Vds is due to the short channel effects and channel length modulation.
Due to these effects the effective length of the channel gets decreased and makes the source and drain aproximately shorted.. and due to this, current flow will increase and breaks the transistor.

But the small increase like 6V and all wont cause the MOS but it somewhat degrades the performance... and it has some effects in output...

But there is no problem for MOS .. I think..

I hope this post helps you,,, .

When Vds is large enough, the strong electrical field will accelerate carrier. Very fast carrier is called hot carrier.
Some of hot carrier will be injected into gate oxide and change the device characteristic (eg. lower Vth will lead to current leakage).

@diarmuid: common Vds ratings are from 50 to 1000V for power MOS used in SMPS. For switching supply rails onboard there are devices of less than 50V, for having as low an Rds as possible. But 5V, I have never seen. Please let us know which device you are talking about, or a link to its datasheet.
@leo_o2: very interesting your explanation. I didn't know drain voltage could affect threshold. And... for years I was wondering why they were called "hot carriers"...

I don't mean drain voltage will effect Vth.
I talked: if hot carrier (with charge) is trapped in gate oxide, Vth will be changed.
Hot means its speed is high.

@leo_o2: You certainly know your hot carrier injection theory! Thanks. Great explanation.

@lw1ecp: Devices are standard CMOS PFETs and NFETs.

Thanks for all the replies guys. Has me much clearer now.

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One final question on hot carrier injection:

Under a strong drain potential, HCI accelerates channel carriers into the oxide.

Therefore, if a device is off is HCI of no concern i.e. if I am violating a VDS spec intended for HCI, that violation
is only valid if the violating FET has a channel formed, in other words is on?

Yes. It is HCI concern if MOS is off.