[SOLVED] Is this STD_LOGIC_VECTOR declaration allowed in VHDL

[Jansi Meena]

Hi friends, I'm new to VHDL and learning slowly.
I found in one code this format

"signal a : std_logic_vector:="00000000";

Where is (x downto 0) stuff?..
Is this type of declaration accepted?

thanks....

 

[TrickyDicky]

are you sure it was a signal? this kind of declaration is allowed for constants, because the initial value sets the length of the array. But be warned, that a vector with no direction automatically becomes a "to" vector.

So in your case (assuming it can take the length for a signal from an initial value), the vector is actually (0 to 7) and not (7 downto 0).

 

[Jansi Meena]

Oh sorry Tricky, this seems to be for constant, I just mis-typed.Thanks
Constant a : std_logic_vector:="00000000";
However in this case, what will be the format of the constant 'a'
Is it "downto" or "to"

Thanks

 

[xtcx]

No doubt,

a : std_logic_vector(0 to 7):="00000000";

Cheers

 

[TrickyDicky]

any array that is specified via initialisation will default to "to".

 

[Jansi Meena]

Thank you. But why do you say this

signal a : std_logic_vector := "00000000";

as Array?...
It is an eight-bit signal right. I have not type declared it as array...Pls can you explain?

 

[TrickyDicky]

std_logic_vector is an array type.

 

[Jansi Meena]

Oh...I've thought this is array

Type a is array (1 to 8) of std_logic_vector(7 downto 0);
signal x : a :=

 

[TrickyDicky]

it is.

But if you look at the declaration of std_logic_vector you will see:

TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic;

 

[Jansi Meena]

Thanks, I got it.
Now one more doubt.
If I declare in any of my array declarations as (NATURAL RANGE <>) instead of (1 to 8) or some finite length what happens?. How much depth my signal will get in such case?. I can not see any range in this (NATURAL RANGE <>). HOw does the tool guess the depth?. Any idea?.

 

[TrickyDicky]

when you declare an array type, you have two options:
1. give it a fixed range, so the array length is always fixed.
2. give the range specficiation, so the length is set when it is declared.

So for one:

type my_array_t is array(1 to 8) of integer;
signal sig : my_array_t;

This is always length 8, the user cannot set the length

type my_array_t is array(natural range <>) of integer;
signal sig1 : my_array_t(1 to 8);
signal sig0 : my_array_t(71 downto 0);

The length is set when the signal is declared. The type in the array bounds of the type declaration limits what the user can do. So above, you could not use -ve numbers, because the type was declared using a natural. If you decalred the range as integer, you could use any integer.

type my_array_t is array(integer range <>) of integer;
signal sig0 : my_array_t(7 downto -8); --length 16
signal sig1 : my_array_t(-100 to 99) ; --length 200

But VHDL allows you to use practically any integer or enumerated type in the range bounds. so if you really wanted, you could do this:

signal my_array_t is array(std_logic range <>) of integer;
signal sig0 : my_array_t('U' to '-'); --length 9

and you use std_logic as the array index:

sig0( '1' ) <= 77;
sig0( 'H' ) <= 99;

 

[Jansi Meena]

Thanks for the brief. But this is the first time, I'm heard about neg index in array(-8 to 7). What's the use?,is it synthesizable? too?

 

[TrickyDicky]

if you look at the declaration of std_logic_vector, you see that it uses natural, so you cannot use -ve number in std_logic_vector.
But for your own arrays, -ve numbers are not a problem.
The new fixed point types sfixed and ufixed use integer range to make it easy to see the separation between integer and fractional parts of a number.

 

[Jansi Meena]

Thank you....

 

[verylsi]

Well Negative numbers are synthesizable , the negative integers are converted to two's compliment of the binary equivalent.

 

[Jansi Meena]

Yes, but what exactly i am asking is like this statement allowed for synthesize?
data <= my_array(-5)

 

[TrickyDicky]

Yes, theres nothing wrong with that.
An index is just a method of switching a mux or addressing a ram. The value doesnt really matter - its a load of bits at the end of the day. If making it -ve in VHDL code makes it easier for you to read, then use the -ve index.

 

[xtcx]

yes, only rational, fractional and algebraic numbers are not allowed. Even when you declare my_array(-2), the tool will use your whole index (-8 to 8) as 0 to 16 only. It is only for the pleasure of human eye

Cheers

 

[TrickyDicky]

Please define what you mean by rational, fractional and algebraic?

The tool will actually use -8 to 7, and use them as -8 to 7, not 0 to 15.

 

[Jansi Meena]

Also, (-8 to 7) is indexed -8 to 7 only but this is just equivalent to raw 16 bits still, the neg index is just for the convenience?. For the Hardware logic, 0 to 15 or -8 to 7 is no different?