Is this statement in error? (verilog timescale statement)

I copied the below off of some slides from my class but I don't understand the values in parenthesis (simulation time units). Are these values in error? The third example looks correct, but the first two don't (i.e. the value given in simulation time units). What am I not getting about the use of timescale here? TIA for your input --


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In other words - starting with the third example, 100fs goes into 1.23 ps 12 times -- that makes sense. But the first two examples don't seem to follow that logic. I would expect the first one to say 10ps goes into 1.23 ns 123 times, but it says 12300 simulation times units. Same with the second example, 123 ns at a 1ns precision should be 123 simulation time units right? - I don't understand how those values for simulation time are calculated.

See if what I wrote here helps you understand.

dave, thanks for your response but I still am not sure that the simulator time units written above are correct. Are you saying that you agree with the values written in parens in the above code? If so then I am still confused - otherwise there must be a mistake. Thanks again --

The values you wrote in parens are indeed the correct values. They are all based on the fact that the simulator uses the smallest time precision (100 fs in this case) for the entire simulation. So taking the first part:


In this case #1.23 means 1.23*1ns = 1.23 ns. And the precision? Well, the 10 ps precision HERE is conveniently ignored, because later on you have a timescale directive with 100 fs precision. And because that 100 fs (the one above module3) is the smallest, the simulator uses a 100 fs time precision. And it so happens that 1.23 ns == 12300*100fs, so all is well.

Ahhh, I see ok I was not getting the whole precision override thing - daves post did say that but I blew past it. I didn't realize it overrides everything not just the module it's in, but that would make sense.

Many thanks to both of you for your answers