is this race condition? why?

Hi.

I'm trying to study about race condition.
So I have been looking the following code.
But I don't know whether race condition or not.
So would you please let me know why does this race condition?


module*race();*
wire*p;*
reg*q;*
assign*p*=*q;*

initial*begin*
q*=*1;*
#1*q*=*0;*
$display(p);*
end*
endmodule*

Your example defines two processes:

1. the assign statement
2. the initial block

A continuous assign statement defines a process that waits for a change in any signal on the RHS. When a changes occurs, it evaluates the expression on the RHS and makes an assignment to the LHS. Then it goes back to waiting for another change.
An initial block defines a process that starts executing a block of procedural statements at time 0. when that block is over, the process terminates. Your example initial block has three statements:

1. an assignment at time 0,
2. wait 1 time unit for another assignment,
3. and then a $display statement.

Verilog defines a sequential execution order of statements within a begin/end block, however the ordering of statements between multiple processes is undetermined. So whether the continuous assignment process does its assignment between statements 2 or 3 is a race condition.

You could use $strobe or put another delay in front of the $display to eliminate the race.