Is this acceptable? - vias under component? - small package TQFP

[aliyesami]

is this acceptable ? - vias under component? - small package TQFP

looks like a terrible design to me but how on earth people can manually route on such a small package TQFP.
are vias allowed under a micro ?

 

[Aussie Susan]

re: is this acceptable ? - vias under component? - small package TQFP

Manually routed PCBs for devices such as this (try 144-pin packages sometime!!!) and it is certainly possible - with patients.
In that layout, I would be a little concerned about the clearance tolerances for some of those vias as there does seem to be ways to move them away from the chip pins without too much effort.
As for via's under a chip, I have used them but make sure that the chip does not have a 'pad' under it that would short them out.
Susan

 

[aliyesami]

Re: is this acceptable ? - vias under component? - small package TQFP

i have managed to come so far ,, am I going in right direction ?

 

[Kick]

Re: is this acceptable ? - vias under component? - small package TQFP

Yes, you can place vias under this component. But be careful there should be a clearance between different net vias and Via to pad.

 

[FvM]

Re: is this acceptable ? - vias under component? - small package TQFP

i have managed to come so far, am I going in right direction ?

Right - so far. I see that you already reduced the via size which is reasonable and helpful to fit the routing.

A possible problem can be seen in the initial post's screenshot, cutting the ground plane with too small residual connections.

 

[KlausST]

Re: is this acceptable ? - vias under component? - small package TQFP

Hi,

The picture of post#1 is a typical EAGLE autorouter result when no information is given to the autorouter about the signal parameters.
So it routes like every signal has the same signal parameters than the other.
***

In general i see no problems with vias under a TQFP package...
For me it's very usual.
***

Routing such layouts per hand is also usual for me.
Athough I use EAGLE and I have the autorouter module, I use it very seldom.
***

For sure the layout of post#3 is better...
Here you take care of the power supply lines. As long as you don't have to drill every single hole on your own, you could connect every GND connection with short wires and a via to the GND plane.
***

It seems to be a microcontroller, maybe an AVR.
I recommend to put a small ceramic C at each supply pin. With short connections..
The same is with AVCC, AREF
and take spicial care with the ADC signals..if you have...

On the left side, there is the Xtal with the R and Cs. Most probably this is the circuit with the highest frequency on your PCB. Therefore I'd try to keep this signals as short as possible and avoid vias in the signal lines.

On the left side bottom, there is a vertical trace, it completely splits the GND plane. Try to move it or keep it short, so that the GND plane is most solid.

The same is with the bottom signal lines on the right side....if you move the traces on the top side to the right, very close to the connectors, then the trace length on the bottom can be short.

Added:
Your trace width is small... usually there is no need to go below 8 mils...even 10 mils should be possible.

Hope that helps

Klaus

 

[aliyesami]

Re: is this acceptable ? - vias under component? - small package TQFP

Yes, you can place vias under this component. But be careful there should be a clearance between different net vias and Via to pad.

what should be the cleareance ? I think now its about 10 mils

- - - Updated - - -

Hi,

The picture of post#1 is a typical EAGLE autorouter result when no information is given to the autorouter about the signal parameters.
So it routes like every signal has the same signal parameters than the other.
***

In general i see no problems with vias under a TQFP package...
For me it's very usual.
***

Routing such layouts per hand is also usual for me.
Athough I use EAGLE and I have the autorouter module, I use it very seldom.
***

For sure the layout of post#3 is better...
Here you take care of the power supply lines. As long as you don't have to drill every single hole on your own, you could connect every GND connection with short wires and a via to the GND plane.
***

It seems to be a microcontroller, maybe an AVR.
I recommend to put a small ceramic C at each supply pin. With short connections..
The same is with AVCC, AREF
and take spicial care with the ADC signals..if you have...

On the left side, there is the Xtal with the R and Cs. Most probably this is the circuit with the highest frequency on your PCB. Therefore I'd try to keep this signals as short as possible and avoid vias in the signal lines.

On the left side bottom, there is a vertical trace, it completely splits the GND plane. Try to move it or keep it short, so that the GND plane is most solid.

The same is with the bottom signal lines on the right side....if you move the traces on the top side to the right, very close to the connectors, then the trace length on the bottom can be short.

Added:
Your trace width is small... usually there is no need to go below 8 mils...even 10 mils should be possible.

Hope that helps

Klaus

Thanks Klaus I will follow your advise .
Although my via seperation is around 10mil but my net lines width is 0.1524 mm which is 6mils , is that too thin ? or can i live with it ?

 

[Aussie Susan]

Re: is this acceptable ? - vias under component? - small package TQFP

You also need to check the tolerances that the PCB fabricator can deliver. They typically have information on their web sites about how close traces can be to other things and how thin the traces can be etc..
Susan

 

[aliyesami]

Re: is this acceptable ? - vias under component? - small package TQFP

here is my ground plane which lines I should move ? can you please point it out ? I dont have any islands on it so should'nt it be fine?

 

[KlausST]

Re: is this acceptable ? - vias under component? - small package TQFP

Hi,

Yes, i think it was the Vcc line. Maybe yo could shorten it and route a bit more on the top.
But it was more a general statement..to keep the GND plane as solid as possible.
It also depends on the routed signals (frequency, current, voltage) and what devices are on the left and the right side of the trace.

Klaus

 

[ArticCynda]

Re: is this acceptable ? - vias under component? - small package TQFP

It's a good strategy to "tent" the vias under components, i.e. pulling solder mask over them. For components in metal packages such as crystals, this is necessary to prevent short circuits.

 

[marce]

Re: is this acceptable ? - vias under component? - small package TQFP

Not a very good way for reliability.... if there is a danger of a short you do not put a via under a device and you NEVER rely on solder mask as an insulator...

 

[FvM]

Re: is this acceptable ? - vias under component? - small package TQFP

If parts have a conductive bottom side at risk to short vias or traces, there will be a keep-out area in the footprint definition. It's usually suggested in datasheets.

Apart from insufficient insulation properties of solder mask, tenting vias may be unwanted according to DFM rules because it promotes incomplete removal of process chemicals and may reduce long-term PCB reliability. My preferred via type is untented with reduced solder mask opening so that it can be placed next to SMD pads without a risk of draining solder and also available as a test point.

 

[Mattylad]

Re: is this acceptable ? - vias under component? - small package TQFP

IF you can put the vias outside the IC it's better, splitting the GND underneath it is also not a good idea.

 

[marce]

Re: is this acceptable ? - vias under component? - small package TQFP

Agree with FvM on via tenting....
Splitting a ground plane with via's anywhere is a bad idea, under these devices you often don't have a choice so like when placing all vias do it so a web of copper floods between them on power and ground layers where possible....

 

[andre_luis]

Re: is this acceptable ? - vias under component? - small package TQFP

Splitting a ground plane with via's anywhere is a bad idea

The spreading of vias along the plane a priori should be appropriate to reduce long paths of ground among layers, which could make the board less sensitive to induced EMI.

 

[FlapJack]

Re: is this acceptable ? - vias under component? - small package TQFP

It's a good strategy to "tent" the vias under components, i.e. pulling solder mask over them. For components in metal packages such as crystals, this is necessary to prevent short circuits.

I bought some commercial data acquisition boards that ran traces under metal packages. 3 out of 5 boards failed in 2 weeks with shorts.

 

[andre_luis]

Re: is this acceptable ? - vias under component? - small package TQFP

It's a good strategy to "tent" the vias under components, i.e. pulling solder mask over them. For components in metal packages such as crystals, this is necessary to prevent short circuits.

At this case in particular, vias under metallic components should be even avoided. The thickness of the solder mask is in the range of microns, perhaps violating many electrical clearance constranints.

 

[EngineerMike]

Re: is this acceptable ? - vias under component? - small package TQFP

If there is no thermal pad on the bottom of the part, you have complete protection against shorting as the part's package will prevent it.

That being said, I prefer to always have all vias and silk screen visible after assembly is complete, so any issues can be easily detected if they arise.

 

[marce]

Re: is this acceptable ? - vias under component? - small package TQFP

Talking about ground plane slots caused by vias NOT connected to the ground plane....