Is there some tools for convert VHDL file to verilog file?

[clivechen]

I am not familiar with VHDL language, But i need to use a VHDL core, I want to convert it to verilog file to understand it. Is there some tools can help me?
I search it in Google, but lots of softwares can't be download,
Can anybody give me a URL, or send me the software
thank you in advance!
clive

 

[nand_gates]

Re: Is there some tools for convert VHDL file to verilog fil

X-HDL is a powerful, "smart" bi-directional translation solution for VHDL and Verilog projects. X-HDL translates netlists, RTL code and many behavioural-level constructs with no requirement for special coding style or translation-control considerations. By performing "smart" translations without converting to an intermediate format, X-HDL retains all source code comments, retains logic structure and easily handles VHDL packages and multiple architectures per entity. Many language incompatibilities such as Verilog multiple assigned wires, Verilog blocking assignments, Verilog system functions, VHDL generates, VHDL user-defined types and VHDL records are all handled completely automatically.