Is there FPGA bootstrap code like a processors?

[delay]

FPGA bootup code

Hello all,

Is there any such thing as FPGA bootstrap code like a processor's?

When implementing large designs should I just load the bitstream from
an external EPROM with the design only in it or should there be some powerup diagnostic routines as GSR, code version etc. used to indicate the device has just come alive? In this sense, what else could be made part of startup code?

Thanks,

Delay (delayed by technology)

 

[davyzhu]

FPGA bootup code

Hello delay,

In FPGA, it is named as 'Configuration', when you test your unstable design ,you may download bit through JTAG wire, after you get a stable version of the design, you can download it to PROM or FLASH(maybe controled by a CPLD ), once you reset the FPGA, the code can be download to FPGA automatically.
For more details, you may refer to Xilinx's userguide and datasheet, search for section 'configuration'.

Cheers,
Davy

 

[tlp71@hotmail.com]

Re: FPGA bootup code

the only way to have a fpga that boostrap is to use a OTP FPGA or the newest Flash FGA (actel and Cypress).
In OTP case you can't upgrade your code, in flash mode may be possible but is not easy