Is there anything wrong with the structure of the clock gating cell ?

[owen_li]

Hi guys.

When I read the power compiler user guide, I find there maybe something wrong with the clock gating structure diagram.
1> I think the latch in the clock gating cell should high level sensitive. If not, it can not prevent the glitch coming from the proceeding logic
2> I think this clock gating cell is used to drive the negative trigger registers.
But in the user guide, it shows the positive trigger register.

Can you give me some ideas ? thanks!
Btw, this diagram is at the chapter 7 of power compiler user guide.

 

[lostinxlation]

Toally opposite.
Unless you want to flip the polarity of the clock, using low through latch is a right thing to do, otherwise you'll get a glitch.
Draw the timing diagram by yourself and you'll know why it has to be a low through latch.

 

[owen_li]

Sorry, this is the diagram. THanks!

 

[lostinxlation]

OK, I got what you mean. I was thinking about a clock gating cell that uses an AND gate..
you are right. it may cause a glitch IF the timing isn't done right... i.e. if EN doesn't settle before the falling edge of the clock, you'll get a glitch, however, the article is aware of that issue.. Looking at the timing diagram, it is setting a setup timing with respect to falling edge, so that those who wrote this article assumes that you'll meet this setup time.
I think it is safer to use high through latch in this case, as you said.

 

[owen_li]

Thanks for your quick reply, lostinxlation.
So, Do you think there is something wrong with the clock gating structure ?
In my opinion, the latch who feeding to the AND gate should high level sensitive, then it can prevent the glitch coming when the CLK is @ low.
second, the clock generated by the clock gating should feed to the negative trigger registers.

Do you agree with my points ?

Thanks again.

 

[lostinxlation]

I don't think the structure is wrong. It just requires a certain setup time to meet. Not sure why they use low-thru latch for this, may be the logic driving EN is neg edge driven and want to give it a full cycle ? I don't know.
I think using high-thru latch is safer in this case in terms of the glitch avoidance, but the type of clock gating cells to use depends on the circumstances that clock gating cell is used in. so hard to say what is the best.