The low-power design flow upon which this SoC was developed, and which is incorporated in the Reference Design Flow
The flow included:
• Cadence Encounter RTL Compiler, as well as other synthesis tools
• Cadence Incisive Unified Simulator and Encounter Conformal Low Power for verification
• Fujitsu intelligent power switch capability, which estimates the requirements for power switches before implementation with attention to noise reduction.
• The tool inserts the right number of power switches to reduce noise while preserving performance, mitigating the effects of rush currents.
This software includes analysis and parameter tables which are based on Fujitsu’s knowledge of process/voltage parameters, switching times, cell and gate requirements, and empirical results from previous chip
• Cadence SoC Encounter
RTL-to-GDSII System for power-aware physical implementation;
This includes an automatic always-on switch insertion, a capability developed in cooperation between Fujitsu and Cadence that is now part of • • Encounter technology
• A Fujitsu proprietary power switch insertion tool, which supports non-rectilinear shaped physical power domains, with an easy graphical user interface (GUI) and full integration with Encounter technology