Hi,
In theory it may not have any problem, but in reality you are creating extra parasitic RC in series.
Your N-well is acts as high resistance in series with active capacitor. (very prone to substrate noise). That is why, this kind of dummy's are avoided where critical signals are routed.
I'd think the additional parasitic cap due to the grounded PMOS is small/negligible compared to the n-well-substrate parasitic cap. So it shouldn't change a lot.
sorry,I may not give reference for this...but, still, i'll tell, PMOS dummy's never used in the lower rail. ( here S,D are connected to GND)( capacitive benifit mentioned may not available here).But it will be vulnerable to breakdown and leakage current may increase. You may find this in any of layout designed in <180nm.
thanks to all of you!
As S,D and G are all connected to gnd, the dummy PMOS is worked as a decouple capacitor and will not affect the signal path, and the only disadvantage is the leakage current, am I right?
thanks to all of you!
As S,D and G are all connected to gnd, the dummy PMOS is worked as a decouple capacitor and will not affect the signal path, and the only disadvantage is the leakage current, am I right?
Hi Chao,
One thing need to understand that, dummys should not be used in active state, (dummy PMOS gate should not be at lower potential and Dummy NMOS gate in higher potential.)
Next PMOS dummys are used in the upper rail voltage ( D, S are shorted to VDD) while NMOS dummys are used in the lower rail. This is the best way to use dummys.
PMOS dummys are used in the upper rail voltage ( D, S are shorted to VDD) while NMOS dummys are used in the lower rail. This is the best way to use dummys.
Source followers are different case, (where Source of the dummy is connected to signal level while others follow the same idea.)
Aprt from all that , You don't see , where actually we place PMOS dummy, and what is the benefit for using GND.
PMOS dummy may be used beside PMOS active transitors, ( and I don't see much application where you need to connect PMOS directly to ground.)
E.g. a PMOS cap in inversion state -- a very effective (high cap/area) capacitor for rail decoupling & LF filter applications, s. below. Shouldn't be labeled as dummy, either.
The overwhelming reason why dummy PMOS is tied to supply rather than gnd is simply because the routing would be more convenient from the well tapping of the n-well. There is no convincing reasons that tieing it to gnd will give any issues.