is there any methdology about verification amba bus?

u24c02 · Mar 19, 2014

Hi

I have generate amba bus by amba designer. So i need verification of this bus.the bus just axi bus.

does anyone knows how to verify this bus?

imbichie · Mar 19, 2014

There are verification IP's availbale from cadence, Altera, xilinx etc...
I dont know more about the licenses and all

u24c02 · Mar 19, 2014

What is BFM?

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imbichie said:
There are verification IP's availbale from cadence, Altera, xilinx etc...
I dont know more about the licenses and all

Thanks, what is BFM?

imbichie · Mar 19, 2014

BFM : Bus Functional Model

harerama · Mar 19, 2014

Hi.

we can verify using system verilog, If u need methodlogy u have to go ovm or uvm.

For basic examples for system verilog check in
http://testbench.in/TB_00_INDEX.html.

u24c02 · Mar 20, 2014

is that free??

harerama said:
Hi.

we can verify using system verilog, If u need methodlogy u have to go ovm or uvm.

For basic examples for system verilog check in
http://testbench.in/TB_00_INDEX.html.

is there any methdology about verification amba bus?

u24c02

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is there any methdology about verification amba bus?

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