is there any Example code for Microchip ENC28j60 ethernet controller Chip?

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Port Map

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Hi,

I want to use ENC28j60 chip to send data from PC to FPGA using TCP protocol.

Does any one know, Is there any example VHDL/Verilog or Microblaze code for this work?

I'll be so thankful for replies.
 

There is a reasonable library out there from microchip (can't believe I just said that), which you then would have to port to microblaze.
 

Very thanks for your replies. I get the library.
Now,
Is that library ready to be used in Microblaze? or I should change it for use?
 

Microchip ENC28J60 ethernet driver (MAC + PHY) program
may be helpful
**broken link removed**
 

I would be very much surprised if a microchip library worked as is on microblaze. So yes, you will have to make some changes. "Which ones?" I hear you ask in a predictable fashion. "Well, the required ones you are going to find about as part of your work" I then reply.

What you can do is grab a few ports of it floating around on the internet, then do a diff for some inspiration.
 
can anyone tell where can I find the verilog code for the same.. (I am using xc3s50)

thanks in advance
 

My controller not only needs to do this function. It is just one of them. I think it would be less memory consuming if it is direct implementation using verilog. correct me if I am wrong.

will be easy to learn how it is implemented in softcore mcu and convert it to verilog?

I have a code for the same as C libraries (used for microcontroller). Is there a way to convert them to verilog?

my questions may be silly bcoz I am new to this and have very little idea about them.
 

Port Map said:
Hi,

I want to use ENC28j60 chip to send data from PC to FPGA using TCP protocol.

Does any one know, Is there any example VHDL/Verilog or Microblaze code for this work?

I'll be so thankful for replies.
Click to expand...


Hey hi, I want to do the same just in reverse. I would like to use the ENC28j60 chip to send data from FPGA to PC using TCP protocol. I was wondering if you could help me out. I want to accomplish the procedure mentioned above using Verilog. Hope you can help me. Anyway, thanks in advance.
 
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