Is there an elegant way to generate a pattern of statements?

[houyh]

Sometimes we want to do this in Verilog HDL:

assign outBus[0] = (inBus == 8'h00); 
assign outBus[1] = (inBus == 8'h01); 
assign outBus[2] = (inBus == 8'h02); 
..................................
assign outBus[255] = (inBus == 8'hff);

Or this:

case (State)
    6'd0 : A[0] <= 1; 
    6'd1 : A[1] <= 1; 
    .............
    6'd63 : A[63] <= 1; 
endcase

For both examples, it would be very tedious to repeat every line manually.

For instantiating multiple components, we do have generate statement to simplify the implementation. But it seems not helpful for the examples above.

Indeed, we can use PERL or another script language to generate such a pattern externally. However, the HDL code itself will still be very lengthy.

So, is there a more elegant way to implement the functionality of such a code block without actually using a huge block of codes? Any response will be appreciated.