is there a way to use DLL in VHDL

[mitaka]

vhdl dll

how can i use DLL ( Delay-Locked Loop) in VHDL design for Virtex-E
to double input clock

 

[ch_wen]

dll vhdl

Why don't you take some time to find it from Language Templates in the ISE Project Navigator?


-- DLL 2X and 4X Example
--
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity dll_standard is
port (CLKIN : in std_logic;
RESET : in std_logic;
CLK2X : out std_logic;
CLK4X : out std_logic;
LOCKED: out std_logic);
end dll_standard;

architecture structural of dll_standard is

signal CLKIN_w, RESET_w, CLK2X_dll, CLK2X_g, CLK4X_dll, CLK4X_g : std_logic;
signal LOCKED2X, LOCKED2X_delay, RESET4X, LOCKED4X_dll : std_logic;
signal logic1 : std_logic;

begin

logic1 <= '1';

clkpad : IBUFG port map (I=>CLKIN, O=>CLKIN_w);
rstpad : IBUF port map (I=>RESET, O=>RESET_w);

dll2x : CLKDLL port map (CLKIN=>CLKIN_w, CLKFB=>CLK2X_g, RST=>RESET_w,
CLK0=>open, CLK90=>open, CLK180=>open, CLK270=>open,
CLK2X=>CLK2X_dll, CLKDV=>open, LOCKED=>LOCKED2X);

clk2xg : BUFG port map (I=>CLK2X_dll, O=>CLK2X_g);

rstsrl : SRL16 port map (D=>LOCKED2X, CLK=>CLK2X_g, Q=>LOCKED2X_delay,
A3=>logic1, A2=>logic1, A1=>logic1, A0=>logic1);

RESET4X <= not LOCKED2X_delay;

dll4x : CLKDLL port map (CLKIN=>CLK2X_g, CLKFB=>CLK4X_g, RST=>RESET4X,
CLK0=>open, CLK90=>open, CLK180=>open, CLK270=>open,
CLK2X=>CLK4X_dll, CLKDV=>open, LOCKED=>LOCKED4X_dll);


clk4xg : BUFG port map (I=>CLK4X_dll, O=>CLK4X_g);
lckpad : OBUF port map (I=>LOCKED4X_dll, O=>LOCKED);

CLK2X <= CLK2X_g;
CLK4X <= CLK4X_g;

end structural;