Is there a way to fix it with Net-delay through EDA to meet Hold violations?

Status
Not open for further replies.

Collang2

Junior Member level 3
Joined
Jun 11, 2021
Messages
25
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
314
I am doing PnR and Timing ECO(ICC2, PT).
I want to do a hold fix.

However, the cell has a corner variation greater than the net delay. I know how to give net delay through manual work(insert buffer..), but I want to automate using EDA Tool.
 

Solution
Q
"cell has a corner variation greater than net delay"
Can you elaborate?

If you have a hold violation, you could find all failing D pins, then add buffers that will fix those violations (without violating setup ofc) on those D pins. then do a quick legalize and eco route on those cells?

This could be done in a for loop. Another way i have used in the past, fix eco hold or a similar command in PT itself where you give it allowed buffers , list of failing endpoints, setup margin to maintain etc..
Sort by date Sort by votes
"cell has a corner variation greater than net delay"
Can you elaborate?

If you have a hold violation, you could find all failing D pins, then add buffers that will fix those violations (without violating setup ofc) on those D pins. then do a quick legalize and eco route on those cells?

This could be done in a for loop. Another way i have used in the past, fix eco hold or a similar command in PT itself where you give it allowed buffers , list of failing endpoints, setup margin to maintain etc..
 

Upvote 0 Downvote
Solution
Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…