[SOLVED] Is there a way to exclude/block shallow Trench Isolation (STI) from getting applied

[dinos7]

Hi guys!,
My circuit can't tolerate change in threshold voltage caused by STI. There is a workaround: if I increase source/drain to channel distance then STI doesn't change the threshold voltage but there are other adverse effects due to increased S/D area.
So I am looking for a way to exclude/block shallow Trench Isolation (STI) from getting applied next to source/drain by the foundary.
Thanks.

 

[dick_freebird]

Not knowing what technology (and probably not using
it anyhow) I'd suggest first looking into the STI mask
fab Booleans, which should be described somewhere in
your PDK docs. Ask the foundry if you don't find this.
It will tell you everything that goes into the STI mask
and one of these may be a "block" layer.

A question is, what ends up between the edge of
active and the new location of STI? And what does
it do? Since this is abnormal to the foundry, you may
get zero help in predicting and no prior data.

If you're talking about "unusual environments" as
your VT shift concern implies, I'd be concerned about
proving that your edge leakage is any better with
STI pushed out away from active - you would still
have some thick oxide over the device edge, to
cause similar trouble.

If you're just talking strain effects, and these are
making devices unstable or unrepeatable, maybe you
want a better foundry that has these in hand.

 

[dinos7]

From the foundry, I just found there is no way to block STI. Since I didn't account the effect of STI earlier in my simulation , I decide to block the STI instead of redesigning the circuit. But redesigning is the only option now, it seems. Thanks for your suggestions dick_freebird