Is there a way to constrain signal logic value in DC

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iamluqi

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Say there is a bus signal A[1:0], and designer knows later after RTL coding that the valid value for signal A is 2'b00, 2'b01, 2'b10, but not 2'b11. Is there anyway to set this signal value constraint so that DC knows 2'b11 is dont-care input and help the logic optimization? I found DC cmds lilke set_logic_one/zero/dc, but no more advanced one for this purpose.
 

do you expect to win something on the gate count?
 
Theoretically there would be some win in gate count, isnt it?
 

That really depend on the logic , the designer have some logic when A=11? If yes you could comment it to see the area improvement, so far I don't known how to exclude a case like your question. Or you could define an enumerate with only the three acceptable cases, but that need to change the code
 

if you don't want to change the code , it may be difficult!
 

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